1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013 Marek Vasut <marex@denx.de> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx53-m53.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Aries/DENX M53EVK"; 11*4882a593Smuzhiyun compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun display1: disp1 { 14*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 15*4882a593Smuzhiyun interface-pix-fmt = "bgr666"; 16*4882a593Smuzhiyun pinctrl-names = "default"; 17*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu_disp1>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun display-timings { 20*4882a593Smuzhiyun 800x480p60 { 21*4882a593Smuzhiyun native-mode; 22*4882a593Smuzhiyun clock-frequency = <31500000>; 23*4882a593Smuzhiyun hactive = <800>; 24*4882a593Smuzhiyun vactive = <480>; 25*4882a593Smuzhiyun hfront-porch = <40>; 26*4882a593Smuzhiyun hback-porch = <88>; 27*4882a593Smuzhiyun hsync-len = <128>; 28*4882a593Smuzhiyun vback-porch = <33>; 29*4882a593Smuzhiyun vfront-porch = <9>; 30*4882a593Smuzhiyun vsync-len = <3>; 31*4882a593Smuzhiyun vsync-active = <1>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun port { 36*4882a593Smuzhiyun display1_in: endpoint { 37*4882a593Smuzhiyun remote-endpoint = <&ipu_di1_disp1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun backlight { 43*4882a593Smuzhiyun compatible = "pwm-backlight"; 44*4882a593Smuzhiyun pwms = <&pwm1 0 3000>; 45*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 46*4882a593Smuzhiyun default-brightness-level = <6>; 47*4882a593Smuzhiyun power-supply = <®_backlight>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun leds { 51*4882a593Smuzhiyun compatible = "gpio-leds"; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&led_pin_gpio>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun user1 { 56*4882a593Smuzhiyun label = "user1"; 57*4882a593Smuzhiyun gpios = <&gpio2 8 0>; 58*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun user2 { 62*4882a593Smuzhiyun label = "user2"; 63*4882a593Smuzhiyun gpios = <&gpio2 9 0>; 64*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun regulators { 69*4882a593Smuzhiyun compatible = "simple-bus"; 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <0>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun reg_usbh1_vbus: regulator@3 { 74*4882a593Smuzhiyun compatible = "regulator-fixed"; 75*4882a593Smuzhiyun reg = <3>; 76*4882a593Smuzhiyun regulator-name = "vbus"; 77*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 78*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 79*4882a593Smuzhiyun gpio = <&gpio1 2 0>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun reg_usb_otg_vbus: regulator@4 { 83*4882a593Smuzhiyun compatible = "regulator-fixed"; 84*4882a593Smuzhiyun reg = <4>; 85*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 86*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 87*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 88*4882a593Smuzhiyun gpio = <&gpio1 4 0>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun sound { 93*4882a593Smuzhiyun compatible = "fsl,imx53-m53evk-sgtl5000", 94*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 95*4882a593Smuzhiyun model = "imx53-m53evk-sgtl5000"; 96*4882a593Smuzhiyun ssi-controller = <&ssi2>; 97*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 98*4882a593Smuzhiyun audio-routing = 99*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 100*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 101*4882a593Smuzhiyun "LINE_IN", "Line In Jack", 102*4882a593Smuzhiyun "Headphone Jack", "HP_OUT", 103*4882a593Smuzhiyun "Ext Spk", "LINE_OUT"; 104*4882a593Smuzhiyun mux-int-port = <2>; 105*4882a593Smuzhiyun mux-ext-port = <4>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&audmux { 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&can1 { 116*4882a593Smuzhiyun pinctrl-names = "default"; 117*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&can2 { 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can2>; 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&esdhc1 { 128*4882a593Smuzhiyun pinctrl-names = "default"; 129*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 130*4882a593Smuzhiyun cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 131*4882a593Smuzhiyun wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 132*4882a593Smuzhiyun status = "okay"; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&fec { 136*4882a593Smuzhiyun pinctrl-names = "default"; 137*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 138*4882a593Smuzhiyun phy-mode = "rmii"; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&i2c1 { 143*4882a593Smuzhiyun pinctrl-names = "default"; 144*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun sgtl5000: codec@a { 148*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 149*4882a593Smuzhiyun reg = <0x0a>; 150*4882a593Smuzhiyun #sound-dai-cells = <0>; 151*4882a593Smuzhiyun VDDA-supply = <®_3p2v>; 152*4882a593Smuzhiyun VDDIO-supply = <®_3p2v>; 153*4882a593Smuzhiyun clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&i2c3 { 158*4882a593Smuzhiyun pinctrl-names = "default"; 159*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&iomuxc { 164*4882a593Smuzhiyun pinctrl-names = "default"; 165*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun imx53-m53evk { 168*4882a593Smuzhiyun pinctrl_usb: usbgrp { 169*4882a593Smuzhiyun fsl,pins = < 170*4882a593Smuzhiyun MX53_PAD_GPIO_2__GPIO1_2 0x80000000 171*4882a593Smuzhiyun MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 172*4882a593Smuzhiyun >; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 176*4882a593Smuzhiyun fsl,pins = < 177*4882a593Smuzhiyun MX53_PAD_GPIO_4__GPIO1_4 0x000b0 178*4882a593Smuzhiyun >; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun led_pin_gpio: led_gpio { 182*4882a593Smuzhiyun fsl,pins = < 183*4882a593Smuzhiyun MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 184*4882a593Smuzhiyun MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 185*4882a593Smuzhiyun >; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 189*4882a593Smuzhiyun fsl,pins = < 190*4882a593Smuzhiyun MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 191*4882a593Smuzhiyun MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 192*4882a593Smuzhiyun MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 193*4882a593Smuzhiyun MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 194*4882a593Smuzhiyun >; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun pinctrl_can1: can1grp { 198*4882a593Smuzhiyun fsl,pins = < 199*4882a593Smuzhiyun MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 200*4882a593Smuzhiyun MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 201*4882a593Smuzhiyun >; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun pinctrl_can2: can2grp { 205*4882a593Smuzhiyun fsl,pins = < 206*4882a593Smuzhiyun MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 207*4882a593Smuzhiyun MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 208*4882a593Smuzhiyun >; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 212*4882a593Smuzhiyun fsl,pins = < 213*4882a593Smuzhiyun MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 214*4882a593Smuzhiyun MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 215*4882a593Smuzhiyun MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 216*4882a593Smuzhiyun MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 217*4882a593Smuzhiyun MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 218*4882a593Smuzhiyun MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 219*4882a593Smuzhiyun >; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun pinctrl_fec: fecgrp { 223*4882a593Smuzhiyun fsl,pins = < 224*4882a593Smuzhiyun MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 225*4882a593Smuzhiyun MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 226*4882a593Smuzhiyun MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 227*4882a593Smuzhiyun MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 228*4882a593Smuzhiyun MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 229*4882a593Smuzhiyun MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 230*4882a593Smuzhiyun MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 231*4882a593Smuzhiyun MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 232*4882a593Smuzhiyun MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 233*4882a593Smuzhiyun MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 234*4882a593Smuzhiyun >; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 238*4882a593Smuzhiyun fsl,pins = < 239*4882a593Smuzhiyun MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 240*4882a593Smuzhiyun MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 241*4882a593Smuzhiyun >; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 245*4882a593Smuzhiyun fsl,pins = < 246*4882a593Smuzhiyun MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 247*4882a593Smuzhiyun MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 248*4882a593Smuzhiyun >; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun pinctrl_ipu_disp1: ipudisp1grp { 252*4882a593Smuzhiyun fsl,pins = < 253*4882a593Smuzhiyun MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 254*4882a593Smuzhiyun MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 255*4882a593Smuzhiyun MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 256*4882a593Smuzhiyun MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 257*4882a593Smuzhiyun MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 258*4882a593Smuzhiyun MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 259*4882a593Smuzhiyun MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 260*4882a593Smuzhiyun MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 261*4882a593Smuzhiyun MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 262*4882a593Smuzhiyun MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 263*4882a593Smuzhiyun MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 264*4882a593Smuzhiyun MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 265*4882a593Smuzhiyun MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 266*4882a593Smuzhiyun MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 267*4882a593Smuzhiyun MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 268*4882a593Smuzhiyun MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 269*4882a593Smuzhiyun MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 270*4882a593Smuzhiyun MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 271*4882a593Smuzhiyun MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 272*4882a593Smuzhiyun MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 273*4882a593Smuzhiyun MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 274*4882a593Smuzhiyun MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 275*4882a593Smuzhiyun MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 276*4882a593Smuzhiyun MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 277*4882a593Smuzhiyun MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 278*4882a593Smuzhiyun MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 279*4882a593Smuzhiyun MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 280*4882a593Smuzhiyun MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 281*4882a593Smuzhiyun MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 282*4882a593Smuzhiyun MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 283*4882a593Smuzhiyun MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 284*4882a593Smuzhiyun MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 285*4882a593Smuzhiyun >; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 289*4882a593Smuzhiyun fsl,pins = < 290*4882a593Smuzhiyun MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 291*4882a593Smuzhiyun >; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 295*4882a593Smuzhiyun fsl,pins = < 296*4882a593Smuzhiyun MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 297*4882a593Smuzhiyun MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 302*4882a593Smuzhiyun fsl,pins = < 303*4882a593Smuzhiyun MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 304*4882a593Smuzhiyun MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 305*4882a593Smuzhiyun >; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 309*4882a593Smuzhiyun fsl,pins = < 310*4882a593Smuzhiyun MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4 311*4882a593Smuzhiyun MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4 312*4882a593Smuzhiyun MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4 313*4882a593Smuzhiyun MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4 314*4882a593Smuzhiyun >; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&ipu_di1_disp1 { 320*4882a593Smuzhiyun remote-endpoint = <&display1_in>; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&pwm1 { 324*4882a593Smuzhiyun #pwm-cells = <2>; 325*4882a593Smuzhiyun pinctrl-names = "default"; 326*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun}; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun&sata { 331*4882a593Smuzhiyun status = "okay"; 332*4882a593Smuzhiyun}; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun&ssi2 { 335*4882a593Smuzhiyun status = "okay"; 336*4882a593Smuzhiyun}; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun&uart1 { 339*4882a593Smuzhiyun pinctrl-names = "default"; 340*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 341*4882a593Smuzhiyun status = "okay"; 342*4882a593Smuzhiyun}; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun&uart2 { 345*4882a593Smuzhiyun pinctrl-names = "default"; 346*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&uart3 { 351*4882a593Smuzhiyun pinctrl-names = "default"; 352*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 353*4882a593Smuzhiyun status = "okay"; 354*4882a593Smuzhiyun}; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun&usbh1 { 357*4882a593Smuzhiyun pinctrl-names = "default"; 358*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb>; 359*4882a593Smuzhiyun vbus-supply = <®_usbh1_vbus>; 360*4882a593Smuzhiyun phy_type = "utmi"; 361*4882a593Smuzhiyun status = "okay"; 362*4882a593Smuzhiyun}; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun&usbotg { 365*4882a593Smuzhiyun pinctrl-names = "default"; 366*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 367*4882a593Smuzhiyun dr_mode = "otg"; 368*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 369*4882a593Smuzhiyun disable-over-current; 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun}; 372