1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8572 DS Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007-2009 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "mpc8572si-pre.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "fsl,MPC8572DS"; 12*4882a593Smuzhiyun compatible = "fsl,MPC8572DS"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun board_lbc: lbc: localbus@ffe05000 { 19*4882a593Smuzhiyun reg = <0 0xffe05000 0 0x1000>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 22*4882a593Smuzhiyun 0x1 0x0 0x0 0xe0000000 0x08000000 23*4882a593Smuzhiyun 0x2 0x0 0x0 0xffa00000 0x00040000 24*4882a593Smuzhiyun 0x3 0x0 0x0 0xffdf0000 0x00008000 25*4882a593Smuzhiyun 0x4 0x0 0x0 0xffa40000 0x00040000 26*4882a593Smuzhiyun 0x5 0x0 0x0 0xffa80000 0x00040000 27*4882a593Smuzhiyun 0x6 0x0 0x0 0xffac0000 0x00040000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun board_soc: soc: soc8572@ffe00000 { 31*4882a593Smuzhiyun ranges = <0x0 0 0xffe00000 0x100000>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun board_pci0: pci0: pcie@ffe08000 { 35*4882a593Smuzhiyun reg = <0 0xffe08000 0 0x1000>; 36*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 37*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; 38*4882a593Smuzhiyun pcie@0 { 39*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 40*4882a593Smuzhiyun 0x2000000 0x0 0x80000000 41*4882a593Smuzhiyun 0x0 0x20000000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 0x1000000 0x0 0x0 44*4882a593Smuzhiyun 0x1000000 0x0 0x0 45*4882a593Smuzhiyun 0x0 0x10000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pci1: pcie@ffe09000 { 50*4882a593Smuzhiyun reg = <0 0xffe09000 0 0x1000>; 51*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 52*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; 53*4882a593Smuzhiyun pcie@0 { 54*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 55*4882a593Smuzhiyun 0x2000000 0x0 0xa0000000 56*4882a593Smuzhiyun 0x0 0x20000000 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 0x1000000 0x0 0x0 59*4882a593Smuzhiyun 0x1000000 0x0 0x0 60*4882a593Smuzhiyun 0x0 0x10000>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pci2: pcie@ffe0a000 { 65*4882a593Smuzhiyun reg = <0 0xffe0a000 0 0x1000>; 66*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 67*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; 68*4882a593Smuzhiyun pcie@0 { 69*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 70*4882a593Smuzhiyun 0x2000000 0x0 0xc0000000 71*4882a593Smuzhiyun 0x0 0x20000000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun 0x1000000 0x0 0x0 74*4882a593Smuzhiyun 0x1000000 0x0 0x0 75*4882a593Smuzhiyun 0x0 0x10000>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun/* 81*4882a593Smuzhiyun * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings 82*4882a593Smuzhiyun * for interrupt-map & interrupt-map-mask 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun/include/ "mpc8572si-post.dtsi" 86*4882a593Smuzhiyun/include/ "mpc8572ds.dtsi" 87