xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx53-smd.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2011 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun// Copyright 2011 Linaro Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include "imx53.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "Freescale i.MX53 Smart Mobile Reference Design Board";
12*4882a593Smuzhiyun	compatible = "fsl,imx53-smd", "fsl,imx53";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	memory@70000000 {
15*4882a593Smuzhiyun		device_type = "memory";
16*4882a593Smuzhiyun		reg = <0x70000000 0x40000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	gpio-keys {
20*4882a593Smuzhiyun		compatible = "gpio-keys";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun		volume-up {
23*4882a593Smuzhiyun			label = "Volume Up";
24*4882a593Smuzhiyun			gpios = <&gpio2 14 0>;
25*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		volume-down {
29*4882a593Smuzhiyun			label = "Volume Down";
30*4882a593Smuzhiyun			gpios = <&gpio2 15 0>;
31*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&esdhc1 {
37*4882a593Smuzhiyun	pinctrl-names = "default";
38*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc1>;
39*4882a593Smuzhiyun	cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
40*4882a593Smuzhiyun	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun&esdhc2 {
45*4882a593Smuzhiyun	pinctrl-names = "default";
46*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc2>;
47*4882a593Smuzhiyun	non-removable;
48*4882a593Smuzhiyun	status = "okay";
49*4882a593Smuzhiyun};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun&uart3 {
52*4882a593Smuzhiyun	pinctrl-names = "default";
53*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
54*4882a593Smuzhiyun	uart-has-rtscts;
55*4882a593Smuzhiyun	status = "okay";
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&ecspi1 {
59*4882a593Smuzhiyun	pinctrl-names = "default";
60*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
61*4882a593Smuzhiyun	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
62*4882a593Smuzhiyun	status = "okay";
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	zigbee: mc1323@0 {
65*4882a593Smuzhiyun		compatible = "fsl,mc1323";
66*4882a593Smuzhiyun		spi-max-frequency = <8000000>;
67*4882a593Smuzhiyun		reg = <0>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	flash: m25p32@1 {
71*4882a593Smuzhiyun		#address-cells = <1>;
72*4882a593Smuzhiyun		#size-cells = <1>;
73*4882a593Smuzhiyun		compatible = "st,m25p32", "st,m25p", "jedec,spi-nor";
74*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
75*4882a593Smuzhiyun		reg = <1>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		partition@0 {
78*4882a593Smuzhiyun			label = "U-Boot";
79*4882a593Smuzhiyun			reg = <0x0 0x40000>;
80*4882a593Smuzhiyun			read-only;
81*4882a593Smuzhiyun		};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		partition@40000 {
84*4882a593Smuzhiyun			label = "Kernel";
85*4882a593Smuzhiyun			reg = <0x40000 0x3c0000>;
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&esdhc3 {
91*4882a593Smuzhiyun	pinctrl-names = "default";
92*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc3>;
93*4882a593Smuzhiyun	non-removable;
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&iomuxc {
98*4882a593Smuzhiyun	pinctrl-names = "default";
99*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	imx53-smd {
102*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
103*4882a593Smuzhiyun			fsl,pins = <
104*4882a593Smuzhiyun				MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
105*4882a593Smuzhiyun				MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
106*4882a593Smuzhiyun				MX53_PAD_EIM_EB2__GPIO2_30     0x80000000
107*4882a593Smuzhiyun				MX53_PAD_EIM_DA13__GPIO3_13    0x80000000
108*4882a593Smuzhiyun				MX53_PAD_EIM_D19__GPIO3_19     0x80000000
109*4882a593Smuzhiyun				MX53_PAD_KEY_ROW2__GPIO4_11    0x80000000
110*4882a593Smuzhiyun				MX53_PAD_PATA_DA_0__GPIO7_6    0x80000000
111*4882a593Smuzhiyun			>;
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
115*4882a593Smuzhiyun			fsl,pins = <
116*4882a593Smuzhiyun				MX53_PAD_EIM_D16__ECSPI1_SCLK		0x80000000
117*4882a593Smuzhiyun				MX53_PAD_EIM_D17__ECSPI1_MISO		0x80000000
118*4882a593Smuzhiyun				MX53_PAD_EIM_D18__ECSPI1_MOSI		0x80000000
119*4882a593Smuzhiyun			>;
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		pinctrl_esdhc1: esdhc1grp {
123*4882a593Smuzhiyun			fsl,pins = <
124*4882a593Smuzhiyun				MX53_PAD_SD1_DATA0__ESDHC1_DAT0		0x1d5
125*4882a593Smuzhiyun				MX53_PAD_SD1_DATA1__ESDHC1_DAT1		0x1d5
126*4882a593Smuzhiyun				MX53_PAD_SD1_DATA2__ESDHC1_DAT2		0x1d5
127*4882a593Smuzhiyun				MX53_PAD_SD1_DATA3__ESDHC1_DAT3		0x1d5
128*4882a593Smuzhiyun				MX53_PAD_SD1_CMD__ESDHC1_CMD		0x1d5
129*4882a593Smuzhiyun				MX53_PAD_SD1_CLK__ESDHC1_CLK		0x1d5
130*4882a593Smuzhiyun			>;
131*4882a593Smuzhiyun		};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		pinctrl_esdhc2: esdhc2grp {
134*4882a593Smuzhiyun			fsl,pins = <
135*4882a593Smuzhiyun				MX53_PAD_SD2_CMD__ESDHC2_CMD		0x1d5
136*4882a593Smuzhiyun				MX53_PAD_SD2_CLK__ESDHC2_CLK		0x1d5
137*4882a593Smuzhiyun				MX53_PAD_SD2_DATA0__ESDHC2_DAT0		0x1d5
138*4882a593Smuzhiyun				MX53_PAD_SD2_DATA1__ESDHC2_DAT1		0x1d5
139*4882a593Smuzhiyun				MX53_PAD_SD2_DATA2__ESDHC2_DAT2		0x1d5
140*4882a593Smuzhiyun				MX53_PAD_SD2_DATA3__ESDHC2_DAT3		0x1d5
141*4882a593Smuzhiyun			>;
142*4882a593Smuzhiyun		};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun		pinctrl_esdhc3: esdhc3grp {
145*4882a593Smuzhiyun			fsl,pins = <
146*4882a593Smuzhiyun				MX53_PAD_PATA_DATA8__ESDHC3_DAT0	0x1d5
147*4882a593Smuzhiyun				MX53_PAD_PATA_DATA9__ESDHC3_DAT1	0x1d5
148*4882a593Smuzhiyun				MX53_PAD_PATA_DATA10__ESDHC3_DAT2	0x1d5
149*4882a593Smuzhiyun				MX53_PAD_PATA_DATA11__ESDHC3_DAT3	0x1d5
150*4882a593Smuzhiyun				MX53_PAD_PATA_DATA0__ESDHC3_DAT4	0x1d5
151*4882a593Smuzhiyun				MX53_PAD_PATA_DATA1__ESDHC3_DAT5	0x1d5
152*4882a593Smuzhiyun				MX53_PAD_PATA_DATA2__ESDHC3_DAT6	0x1d5
153*4882a593Smuzhiyun				MX53_PAD_PATA_DATA3__ESDHC3_DAT7	0x1d5
154*4882a593Smuzhiyun				MX53_PAD_PATA_RESET_B__ESDHC3_CMD	0x1d5
155*4882a593Smuzhiyun				MX53_PAD_PATA_IORDY__ESDHC3_CLK		0x1d5
156*4882a593Smuzhiyun			>;
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		pinctrl_fec: fecgrp {
160*4882a593Smuzhiyun			fsl,pins = <
161*4882a593Smuzhiyun				MX53_PAD_FEC_MDC__FEC_MDC		0x80000000
162*4882a593Smuzhiyun				MX53_PAD_FEC_MDIO__FEC_MDIO		0x80000000
163*4882a593Smuzhiyun				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK	0x80000000
164*4882a593Smuzhiyun				MX53_PAD_FEC_RX_ER__FEC_RX_ER		0x80000000
165*4882a593Smuzhiyun				MX53_PAD_FEC_CRS_DV__FEC_RX_DV		0x80000000
166*4882a593Smuzhiyun				MX53_PAD_FEC_RXD1__FEC_RDATA_1		0x80000000
167*4882a593Smuzhiyun				MX53_PAD_FEC_RXD0__FEC_RDATA_0		0x80000000
168*4882a593Smuzhiyun				MX53_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
169*4882a593Smuzhiyun				MX53_PAD_FEC_TXD1__FEC_TDATA_1		0x80000000
170*4882a593Smuzhiyun				MX53_PAD_FEC_TXD0__FEC_TDATA_0		0x80000000
171*4882a593Smuzhiyun			>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
175*4882a593Smuzhiyun			fsl,pins = <
176*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT8__I2C1_SDA		0xc0000000
177*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT9__I2C1_SCL		0xc0000000
178*4882a593Smuzhiyun			>;
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
182*4882a593Smuzhiyun			fsl,pins = <
183*4882a593Smuzhiyun				MX53_PAD_KEY_ROW3__I2C2_SDA		0xc0000000
184*4882a593Smuzhiyun				MX53_PAD_KEY_COL3__I2C2_SCL		0xc0000000
185*4882a593Smuzhiyun			>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun		pinctrl_ipu_csi0: ipucsi0grp {
189*4882a593Smuzhiyun			fsl,pins = <
190*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12    0x1c4
191*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13    0x1c4
192*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14    0x1c4
193*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15    0x1c4
194*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16    0x1c4
195*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17    0x1c4
196*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18    0x1c4
197*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19    0x1c4
198*4882a593Smuzhiyun				MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4
199*4882a593Smuzhiyun				MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC   0x1e4
200*4882a593Smuzhiyun				MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC    0x1e4
201*4882a593Smuzhiyun				MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4
202*4882a593Smuzhiyun			>;
203*4882a593Smuzhiyun		};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun		pinctrl_ov5642: ov5642grp {
206*4882a593Smuzhiyun			fsl,pins = <
207*4882a593Smuzhiyun				MX53_PAD_NANDF_WP_B__GPIO6_9   0x1e4
208*4882a593Smuzhiyun				MX53_PAD_NANDF_RB0__GPIO6_10   0x1e4
209*4882a593Smuzhiyun				MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
210*4882a593Smuzhiyun			>;
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
214*4882a593Smuzhiyun			fsl,pins = <
215*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT10__UART1_TXD_MUX	0x1e4
216*4882a593Smuzhiyun				MX53_PAD_CSI0_DAT11__UART1_RXD_MUX	0x1e4
217*4882a593Smuzhiyun			>;
218*4882a593Smuzhiyun		};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
221*4882a593Smuzhiyun			fsl,pins = <
222*4882a593Smuzhiyun				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX	0x1e4
223*4882a593Smuzhiyun				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX	0x1e4
224*4882a593Smuzhiyun			>;
225*4882a593Smuzhiyun		};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
228*4882a593Smuzhiyun			fsl,pins = <
229*4882a593Smuzhiyun				MX53_PAD_PATA_CS_0__UART3_TXD_MUX	0x1e4
230*4882a593Smuzhiyun				MX53_PAD_PATA_CS_1__UART3_RXD_MUX	0x1e4
231*4882a593Smuzhiyun				MX53_PAD_PATA_DA_1__UART3_CTS		0x1e4
232*4882a593Smuzhiyun				MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
233*4882a593Smuzhiyun			>;
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun	};
236*4882a593Smuzhiyun};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun&uart1 {
239*4882a593Smuzhiyun	pinctrl-names = "default";
240*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&uart2 {
245*4882a593Smuzhiyun	pinctrl-names = "default";
246*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
247*4882a593Smuzhiyun	status = "okay";
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&i2c2 {
251*4882a593Smuzhiyun	pinctrl-names = "default";
252*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	codec: sgtl5000@a {
256*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
257*4882a593Smuzhiyun		reg = <0x0a>;
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	magnetometer: mag3110@e {
261*4882a593Smuzhiyun		compatible = "fsl,mag3110";
262*4882a593Smuzhiyun		reg = <0x0e>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	touchkey: mpr121@5a {
266*4882a593Smuzhiyun		compatible = "fsl,mpr121";
267*4882a593Smuzhiyun		reg = <0x5a>;
268*4882a593Smuzhiyun	};
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&i2c1 {
272*4882a593Smuzhiyun	pinctrl-names = "default";
273*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
274*4882a593Smuzhiyun	status = "okay";
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun	accelerometer: mma8450@1c {
277*4882a593Smuzhiyun		compatible = "fsl,mma8450";
278*4882a593Smuzhiyun		reg = <0x1c>;
279*4882a593Smuzhiyun	};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun	camera: ov5642@3c {
282*4882a593Smuzhiyun		compatible = "ovti,ov5642";
283*4882a593Smuzhiyun		reg = <0x3c>;
284*4882a593Smuzhiyun		pinctrl-names = "default";
285*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ov5642>;
286*4882a593Smuzhiyun		assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>,
287*4882a593Smuzhiyun				  <&clks IMX5_CLK_SSI_EXT1_COM_SEL>;
288*4882a593Smuzhiyun		assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>,
289*4882a593Smuzhiyun					 <&clks IMX5_CLK_SSI_EXT1_PODF>;
290*4882a593Smuzhiyun		assigned-clock-rates = <0>, <24000000>;
291*4882a593Smuzhiyun		clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
292*4882a593Smuzhiyun		clock-names = "xclk";
293*4882a593Smuzhiyun		DVDD-supply = <&ldo9_reg>;
294*4882a593Smuzhiyun		AVDD-supply = <&ldo7_reg>;
295*4882a593Smuzhiyun		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
296*4882a593Smuzhiyun		powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun		port {
299*4882a593Smuzhiyun			ov5642_to_ipu_csi0: endpoint {
300*4882a593Smuzhiyun				remote-endpoint = <&ipu_csi0_from_parallel_sensor>;
301*4882a593Smuzhiyun				bus-width = <8>;
302*4882a593Smuzhiyun				hsync-active = <1>;
303*4882a593Smuzhiyun				vsync-active = <1>;
304*4882a593Smuzhiyun			};
305*4882a593Smuzhiyun		};
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun	pmic: dialog@48 {
309*4882a593Smuzhiyun		compatible = "dlg,da9053", "dlg,da9052";
310*4882a593Smuzhiyun		reg = <0x48>;
311*4882a593Smuzhiyun		interrupt-parent = <&gpio7>;
312*4882a593Smuzhiyun		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun		regulators {
315*4882a593Smuzhiyun			ldo7_reg: ldo7 {
316*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
317*4882a593Smuzhiyun				regulator-max-microvolt = <3600000>;
318*4882a593Smuzhiyun			};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun			ldo9_reg: ldo9 {
321*4882a593Smuzhiyun				regulator-min-microvolt = <1250000>;
322*4882a593Smuzhiyun				regulator-max-microvolt = <3650000>;
323*4882a593Smuzhiyun			};
324*4882a593Smuzhiyun		};
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&fec {
329*4882a593Smuzhiyun	pinctrl-names = "default";
330*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec>;
331*4882a593Smuzhiyun	phy-mode = "rmii";
332*4882a593Smuzhiyun	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&ipu_csi0_from_parallel_sensor {
337*4882a593Smuzhiyun	remote-endpoint = <&ov5642_to_ipu_csi0>;
338*4882a593Smuzhiyun	data-shift = <12>; /* Lines 19:12 used */
339*4882a593Smuzhiyun	hsync-active = <1>;
340*4882a593Smuzhiyun	vsync-active = <1>;
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&ipu_csi0 {
344*4882a593Smuzhiyun	pinctrl-names = "default";
345*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ipu_csi0>;
346*4882a593Smuzhiyun};
347