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/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/OK3568_Linux_fs/kernel/drivers/media/common/b2c2/
H A Dflexcop-sram.c28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/OK3568_Linux_fs/u-boot/board/armltd/vexpress/
H A Dvexpress_tc2.c16 #define SCC_BASE 0x7fff0000
24 * The Serial Configuration Controller (SCC) register at address 0x700 in armv7_boot_nonsec_default()
35 return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; in armv7_boot_nonsec_default()
48 return 0;
50 return 0;
54 if (offset < 0) {
60 for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0;
67 while (offset > 0) {
83 return 0;
/OK3568_Linux_fs/u-boot/include/rockchip/
H A Dcrypto_v1.h19 u32 reserved0[(0x80 - 0x24) / 4];
28 u32 reserved1[(0x100 - 0xe8) / 4];
38 u32 reserved2[(0x180 - 0x138) / 4];
45 u32 reserved3[(0x200 - 0x1c0) / 4];
49 u32 reserved4[(0x280 - 0x224) / 4];
52 u32 reserved5[(0x400 - 0x284) / 4];
54 u32 crypto_pka_m[(0x500 - 0x400) / 4];
55 u32 crypto_pka_c[(0x600 - 0x500) / 4];
56 u32 crypto_pka_n[(0x700 - 0x600) / 4];
60 check_member(rk_crypto_reg, crypto_pka_e, 0x700);
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h20 #define EXYNOS_GPIO_ECON_OFFSET 0x700
21 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
22 #define EXYNOS_GPIO_EMASK_OFFSET 0x900
23 #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
24 #define EXYNOS_WKUP_ECON_OFFSET 0xE00
25 #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
26 #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
27 #define EXYNOS7_WKUP_ECON_OFFSET 0x700
28 #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
29 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drenesas,usb2-phy.yaml48 enum: [0, 1] # and 0 is deprecated.
107 reg = <0xee080200 0x700>;
115 reg = <0xee0a0200 0x700>;
/OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh4-202.c23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dsbpcmcia.h42 #define PCMCIA_FCR (0x700 / 2)
44 #define FCR0_OFF 0
45 #define FCR1_OFF (0x40 / 2)
46 #define FCR2_OFF (0x80 / 2)
47 #define FCR3_OFF (0xc0 / 2)
49 #define PCMCIA_FCR0 (0x700 / 2)
50 #define PCMCIA_FCR1 (0x740 / 2)
51 #define PCMCIA_FCR2 (0x780 / 2)
52 #define PCMCIA_FCR3 (0x7c0 / 2)
56 #define PCMCIA_COR 0
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Ddc.h13 /* CMD register 0x000 ~ 0x43 */
15 /* Address 0x000 ~ 0x002 */
22 /* Address 0x008 ~ 0x00a */
29 /* Address 0x010 ~ 0x012 */
36 /* Address 0x018 ~ 0x01a */
43 /* Address 0x028 */
48 /* Address 0x030 ~ 0x033 */
56 /* Address 0x036 ~ 0x03e */
69 /* Address 0x040 ~ 0x043 */
81 /* COM register 0x300 ~ 0x329 */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/
H A Dsbpcmcia.h43 #define PCMCIA_FCR (0x700 / 2)
45 #define FCR0_OFF 0
46 #define FCR1_OFF (0x40 / 2)
47 #define FCR2_OFF (0x80 / 2)
48 #define FCR3_OFF (0xc0 / 2)
50 #define PCMCIA_FCR0 (0x700 / 2)
51 #define PCMCIA_FCR1 (0x740 / 2)
52 #define PCMCIA_FCR2 (0x780 / 2)
53 #define PCMCIA_FCR3 (0x7c0 / 2)
57 #define PCMCIA_COR 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Dsbpcmcia.h43 #define PCMCIA_FCR (0x700 / 2)
45 #define FCR0_OFF 0
46 #define FCR1_OFF (0x40 / 2)
47 #define FCR2_OFF (0x80 / 2)
48 #define FCR3_OFF (0xc0 / 2)
50 #define PCMCIA_FCR0 (0x700 / 2)
51 #define PCMCIA_FCR1 (0x740 / 2)
52 #define PCMCIA_FCR2 (0x780 / 2)
53 #define PCMCIA_FCR3 (0x7c0 / 2)
57 #define PCMCIA_COR 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Dsbpcmcia.h43 #define PCMCIA_FCR (0x700 / 2)
45 #define FCR0_OFF 0
46 #define FCR1_OFF (0x40 / 2)
47 #define FCR2_OFF (0x80 / 2)
48 #define FCR3_OFF (0xc0 / 2)
50 #define PCMCIA_FCR0 (0x700 / 2)
51 #define PCMCIA_FCR1 (0x740 / 2)
52 #define PCMCIA_FCR2 (0x780 / 2)
53 #define PCMCIA_FCR3 (0x7c0 / 2)
57 #define PCMCIA_COR 0
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Ddisplay.h44 #define DPCD_SIZE 0x700
62 #define DPCD_SIZE 0x700
65 #define DP_SET_POWER 0x600
66 #define DP_SET_POWER_D0 0x1
67 #define AUX_NATIVE_WRITE 0x8
68 #define AUX_NATIVE_READ 0x9
70 #define AUX_NATIVE_REPLY_MASK (0x3 << 4)
71 #define AUX_NATIVE_REPLY_ACK (0x0 << 4)
72 #define AUX_NATIVE_REPLY_NAK (0x1 << 4)
73 #define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dcb710.h109 #define cb710_dump_regs(c, d) do {} while (0)
112 #define CB710_DUMP_REGS_MMC 0x0F
113 #define CB710_DUMP_REGS_MS 0x30
114 #define CB710_DUMP_REGS_SM 0xC0
115 #define CB710_DUMP_REGS_ALL 0xFF
116 #define CB710_DUMP_REGS_MASK 0xFF
118 #define CB710_DUMP_ACCESS_8 0x100
119 #define CB710_DUMP_ACCESS_16 0x200
120 #define CB710_DUMP_ACCESS_32 0x400
121 #define CB710_DUMP_ACCESS_ALL 0x700
[all …]

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