1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ROCKCHIP_CRYPTO_V1_H_ 7*4882a593Smuzhiyun #define _ROCKCHIP_CRYPTO_V1_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct rk_crypto_reg { 10*4882a593Smuzhiyun u32 crypto_intsts; 11*4882a593Smuzhiyun u32 crypto_intena; 12*4882a593Smuzhiyun u32 crypto_ctrl; 13*4882a593Smuzhiyun u32 crypto_conf; 14*4882a593Smuzhiyun u32 crypto_brdmas; 15*4882a593Smuzhiyun u32 crypto_btdmas; 16*4882a593Smuzhiyun u32 crypto_brdmal; 17*4882a593Smuzhiyun u32 crypto_hrdmas; 18*4882a593Smuzhiyun u32 crypto_hrdmal; 19*4882a593Smuzhiyun u32 reserved0[(0x80 - 0x24) / 4]; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun u32 crypto_aes_ctrl; 22*4882a593Smuzhiyun u32 crypto_aes_sts; 23*4882a593Smuzhiyun u32 crypto_aes_din[4]; 24*4882a593Smuzhiyun u32 crypto_aes_dout[4]; 25*4882a593Smuzhiyun u32 crypto_aes_iv[4]; 26*4882a593Smuzhiyun u32 crypto_aes_key[8]; 27*4882a593Smuzhiyun u32 crypto_aes_cnt[4]; 28*4882a593Smuzhiyun u32 reserved1[(0x100 - 0xe8) / 4]; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun u32 crypto_tdes_ctrl; 31*4882a593Smuzhiyun u32 crypto_tdes_sts; 32*4882a593Smuzhiyun u32 crypto_tdes_din[2]; 33*4882a593Smuzhiyun u32 crypto_tdes_dout[2]; 34*4882a593Smuzhiyun u32 crypto_tdes_iv[2]; 35*4882a593Smuzhiyun u32 crypto_tdes_key1[2]; 36*4882a593Smuzhiyun u32 crypto_tdes_key2[2]; 37*4882a593Smuzhiyun u32 crypto_tdes_key3[2]; 38*4882a593Smuzhiyun u32 reserved2[(0x180 - 0x138) / 4]; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun u32 crypto_hash_ctrl; 41*4882a593Smuzhiyun u32 crypto_hash_sts; 42*4882a593Smuzhiyun u32 crypto_hash_msg_len; 43*4882a593Smuzhiyun u32 crypto_hash_dout[8]; 44*4882a593Smuzhiyun u32 crypto_hash_seed[5]; 45*4882a593Smuzhiyun u32 reserved3[(0x200 - 0x1c0) / 4]; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun u32 crypto_trng_ctrl; 48*4882a593Smuzhiyun u32 crypto_trng_dout[8]; 49*4882a593Smuzhiyun u32 reserved4[(0x280 - 0x224) / 4]; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u32 crypto_pka_ctrl; 52*4882a593Smuzhiyun u32 reserved5[(0x400 - 0x284) / 4]; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun u32 crypto_pka_m[(0x500 - 0x400) / 4]; 55*4882a593Smuzhiyun u32 crypto_pka_c[(0x600 - 0x500) / 4]; 56*4882a593Smuzhiyun u32 crypto_pka_n[(0x700 - 0x600) / 4]; 57*4882a593Smuzhiyun u32 crypto_pka_e; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun check_member(rk_crypto_reg, crypto_pka_e, 0x700); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /************************ Register bits definition ****************************/ 63*4882a593Smuzhiyun /* CRYPTO_HASH_CTRL */ 64*4882a593Smuzhiyun #define ENGINE_SELECTION_SHA1 0x0 65*4882a593Smuzhiyun #define ENGINE_SELECTION_MD5 0x1 66*4882a593Smuzhiyun #define ENGINE_SELECTION_SHA256 0x2 67*4882a593Smuzhiyun #define HASH_SWAP_DO 0x8 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* CRYPTO_CONF */ 70*4882a593Smuzhiyun #define HR_ADDR_MODE BIT(8) 71*4882a593Smuzhiyun #define BT_ADDR_MODE BIT(7) 72*4882a593Smuzhiyun #define BR_ADDR_MODE BIT(6) 73*4882a593Smuzhiyun #define BYTESWAP_HRFIFO BIT(5) 74*4882a593Smuzhiyun #define BYTESWAP_BTFIFO BIT(4) 75*4882a593Smuzhiyun #define BYTESWAP_BRFIFO BIT(3) 76*4882a593Smuzhiyun #define DESSEL BIT(2) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* CRYPTO_CTRL */ 79*4882a593Smuzhiyun #define TRNG_FLUSH BIT(9) 80*4882a593Smuzhiyun #define TRNG_START BIT(8) 81*4882a593Smuzhiyun #define PKA_FLUSH BIT(7) 82*4882a593Smuzhiyun #define HASH_FLUSH BIT(6) 83*4882a593Smuzhiyun #define BLOCK_FLUSH BIT(5) 84*4882a593Smuzhiyun #define PKA_START BIT(4) 85*4882a593Smuzhiyun #define HASH_START BIT(3) 86*4882a593Smuzhiyun #define BLOCK_START BIT(2) 87*4882a593Smuzhiyun #define TDES_START BIT(1) 88*4882a593Smuzhiyun #define AES_START BIT(0) 89*4882a593Smuzhiyun #define PKA_HASH_CTRL (PKA_FLUSH | HASH_FLUSH) 90*4882a593Smuzhiyun #define PKA_CTRL (PKA_FLUSH | PKA_START) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* CRYPTO_INTSTS */ 93*4882a593Smuzhiyun #define PKA_DONE_INT BIT(5) 94*4882a593Smuzhiyun #define HASH_DONE_INT BIT(4) 95*4882a593Smuzhiyun #define HRDMA_ERR_INT BIT(3) 96*4882a593Smuzhiyun #define HRDMA_DONE_INT BIT(2) 97*4882a593Smuzhiyun #define BCDMA_ERR_INT BIT(1) 98*4882a593Smuzhiyun #define BCDMA_DONE_INT BIT(0) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* CRYPTO_PKA_CTRL */ 101*4882a593Smuzhiyun #define PKA_BLOCK_SIZE_512 0 102*4882a593Smuzhiyun #define PKA_BLOCK_SIZE_1024 1 103*4882a593Smuzhiyun #define PKA_BLOCK_SIZE_2048 2 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif 106