1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Exynos specific definitions for Samsung pinctrl and gpiolib driver. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * http://www.samsung.com 7*4882a593Smuzhiyun * Copyright (c) 2012 Linaro Ltd 8*4882a593Smuzhiyun * http://www.linaro.org 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file contains the Exynos specific definitions for the Samsung 11*4882a593Smuzhiyun * pinctrl/gpiolib interface drivers. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Author: Thomas Abraham <thomas.ab@samsung.com> 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __PINCTRL_SAMSUNG_EXYNOS_H 17*4882a593Smuzhiyun #define __PINCTRL_SAMSUNG_EXYNOS_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* External GPIO and wakeup interrupt related definitions */ 20*4882a593Smuzhiyun #define EXYNOS_GPIO_ECON_OFFSET 0x700 21*4882a593Smuzhiyun #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 22*4882a593Smuzhiyun #define EXYNOS_GPIO_EMASK_OFFSET 0x900 23*4882a593Smuzhiyun #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 24*4882a593Smuzhiyun #define EXYNOS_WKUP_ECON_OFFSET 0xE00 25*4882a593Smuzhiyun #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 26*4882a593Smuzhiyun #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 27*4882a593Smuzhiyun #define EXYNOS7_WKUP_ECON_OFFSET 0x700 28*4882a593Smuzhiyun #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 29*4882a593Smuzhiyun #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 30*4882a593Smuzhiyun #define EXYNOS_SVC_OFFSET 0xB08 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* helpers to access interrupt service register */ 33*4882a593Smuzhiyun #define EXYNOS_SVC_GROUP_SHIFT 3 34*4882a593Smuzhiyun #define EXYNOS_SVC_GROUP_MASK 0x1f 35*4882a593Smuzhiyun #define EXYNOS_SVC_NUM_MASK 7 36*4882a593Smuzhiyun #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ 37*4882a593Smuzhiyun EXYNOS_SVC_GROUP_MASK) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Exynos specific external interrupt trigger types */ 40*4882a593Smuzhiyun #define EXYNOS_EINT_LEVEL_LOW 0 41*4882a593Smuzhiyun #define EXYNOS_EINT_LEVEL_HIGH 1 42*4882a593Smuzhiyun #define EXYNOS_EINT_EDGE_FALLING 2 43*4882a593Smuzhiyun #define EXYNOS_EINT_EDGE_RISING 3 44*4882a593Smuzhiyun #define EXYNOS_EINT_EDGE_BOTH 4 45*4882a593Smuzhiyun #define EXYNOS_EINT_CON_MASK 0xF 46*4882a593Smuzhiyun #define EXYNOS_EINT_CON_LEN 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define EXYNOS_EINT_MAX_PER_BANK 8 49*4882a593Smuzhiyun #define EXYNOS_EINT_NR_WKUP_EINT 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ 52*4882a593Smuzhiyun { \ 53*4882a593Smuzhiyun .type = &bank_type_off, \ 54*4882a593Smuzhiyun .pctl_offset = reg, \ 55*4882a593Smuzhiyun .nr_pins = pins, \ 56*4882a593Smuzhiyun .eint_type = EINT_TYPE_NONE, \ 57*4882a593Smuzhiyun .name = id \ 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ 61*4882a593Smuzhiyun { \ 62*4882a593Smuzhiyun .type = &bank_type_off, \ 63*4882a593Smuzhiyun .pctl_offset = reg, \ 64*4882a593Smuzhiyun .nr_pins = pins, \ 65*4882a593Smuzhiyun .eint_type = EINT_TYPE_GPIO, \ 66*4882a593Smuzhiyun .eint_offset = offs, \ 67*4882a593Smuzhiyun .name = id \ 68*4882a593Smuzhiyun } 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ 71*4882a593Smuzhiyun { \ 72*4882a593Smuzhiyun .type = &bank_type_alive, \ 73*4882a593Smuzhiyun .pctl_offset = reg, \ 74*4882a593Smuzhiyun .nr_pins = pins, \ 75*4882a593Smuzhiyun .eint_type = EINT_TYPE_WKUP, \ 76*4882a593Smuzhiyun .eint_offset = offs, \ 77*4882a593Smuzhiyun .name = id \ 78*4882a593Smuzhiyun } 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ 81*4882a593Smuzhiyun { \ 82*4882a593Smuzhiyun .type = &exynos5433_bank_type_off, \ 83*4882a593Smuzhiyun .pctl_offset = reg, \ 84*4882a593Smuzhiyun .nr_pins = pins, \ 85*4882a593Smuzhiyun .eint_type = EINT_TYPE_GPIO, \ 86*4882a593Smuzhiyun .eint_offset = offs, \ 87*4882a593Smuzhiyun .name = id \ 88*4882a593Smuzhiyun } 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ 91*4882a593Smuzhiyun { \ 92*4882a593Smuzhiyun .type = &exynos5433_bank_type_alive, \ 93*4882a593Smuzhiyun .pctl_offset = reg, \ 94*4882a593Smuzhiyun .nr_pins = pins, \ 95*4882a593Smuzhiyun .eint_type = EINT_TYPE_WKUP, \ 96*4882a593Smuzhiyun .eint_offset = offs, \ 97*4882a593Smuzhiyun .name = id \ 98*4882a593Smuzhiyun } 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ 101*4882a593Smuzhiyun { \ 102*4882a593Smuzhiyun .type = &exynos5433_bank_type_off, \ 103*4882a593Smuzhiyun .pctl_offset = reg, \ 104*4882a593Smuzhiyun .nr_pins = pins, \ 105*4882a593Smuzhiyun .eint_type = EINT_TYPE_WKUP, \ 106*4882a593Smuzhiyun .eint_offset = offs, \ 107*4882a593Smuzhiyun .name = id, \ 108*4882a593Smuzhiyun .pctl_res_idx = pctl_idx, \ 109*4882a593Smuzhiyun } \ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /** 112*4882a593Smuzhiyun * struct exynos_weint_data: irq specific data for all the wakeup interrupts 113*4882a593Smuzhiyun * generated by the external wakeup interrupt controller. 114*4882a593Smuzhiyun * @irq: interrupt number within the domain. 115*4882a593Smuzhiyun * @bank: bank responsible for this interrupt 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun struct exynos_weint_data { 118*4882a593Smuzhiyun unsigned int irq; 119*4882a593Smuzhiyun struct samsung_pin_bank *bank; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /** 123*4882a593Smuzhiyun * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts 124*4882a593Smuzhiyun * generated by the external wakeup interrupt controller. 125*4882a593Smuzhiyun * @nr_banks: count of banks being part of the mux 126*4882a593Smuzhiyun * @banks: array of banks being part of the mux 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun struct exynos_muxed_weint_data { 129*4882a593Smuzhiyun unsigned int nr_banks; 130*4882a593Smuzhiyun struct samsung_pin_bank *banks[]; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); 134*4882a593Smuzhiyun int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); 135*4882a593Smuzhiyun void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); 136*4882a593Smuzhiyun void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); 137*4882a593Smuzhiyun struct samsung_retention_ctrl * 138*4882a593Smuzhiyun exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, 139*4882a593Smuzhiyun const struct samsung_retention_data *data); 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ 142