1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL 5*4882a593Smuzhiyun * You can choose the licence that better fits your requirements. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License 8*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Clock Control Unit 1 (CCU1) clock offsets */ 13*4882a593Smuzhiyun #define CLK_APB3_BUS 0x100 14*4882a593Smuzhiyun #define CLK_APB3_I2C1 0x108 15*4882a593Smuzhiyun #define CLK_APB3_DAC 0x110 16*4882a593Smuzhiyun #define CLK_APB3_ADC0 0x118 17*4882a593Smuzhiyun #define CLK_APB3_ADC1 0x120 18*4882a593Smuzhiyun #define CLK_APB3_CAN0 0x128 19*4882a593Smuzhiyun #define CLK_APB1_BUS 0x200 20*4882a593Smuzhiyun #define CLK_APB1_MOTOCON_PWM 0x208 21*4882a593Smuzhiyun #define CLK_APB1_I2C0 0x210 22*4882a593Smuzhiyun #define CLK_APB1_I2S 0x218 23*4882a593Smuzhiyun #define CLK_APB1_CAN1 0x220 24*4882a593Smuzhiyun #define CLK_SPIFI 0x300 25*4882a593Smuzhiyun #define CLK_CPU_BUS 0x400 26*4882a593Smuzhiyun #define CLK_CPU_SPIFI 0x408 27*4882a593Smuzhiyun #define CLK_CPU_GPIO 0x410 28*4882a593Smuzhiyun #define CLK_CPU_LCD 0x418 29*4882a593Smuzhiyun #define CLK_CPU_ETHERNET 0x420 30*4882a593Smuzhiyun #define CLK_CPU_USB0 0x428 31*4882a593Smuzhiyun #define CLK_CPU_EMC 0x430 32*4882a593Smuzhiyun #define CLK_CPU_SDIO 0x438 33*4882a593Smuzhiyun #define CLK_CPU_DMA 0x440 34*4882a593Smuzhiyun #define CLK_CPU_CORE 0x448 35*4882a593Smuzhiyun #define CLK_CPU_SCT 0x468 36*4882a593Smuzhiyun #define CLK_CPU_USB1 0x470 37*4882a593Smuzhiyun #define CLK_CPU_EMCDIV 0x478 38*4882a593Smuzhiyun #define CLK_CPU_FLASHA 0x480 39*4882a593Smuzhiyun #define CLK_CPU_FLASHB 0x488 40*4882a593Smuzhiyun #define CLK_CPU_M0APP 0x490 41*4882a593Smuzhiyun #define CLK_CPU_ADCHS 0x498 42*4882a593Smuzhiyun #define CLK_CPU_EEPROM 0x4a0 43*4882a593Smuzhiyun #define CLK_CPU_WWDT 0x500 44*4882a593Smuzhiyun #define CLK_CPU_UART0 0x508 45*4882a593Smuzhiyun #define CLK_CPU_UART1 0x510 46*4882a593Smuzhiyun #define CLK_CPU_SSP0 0x518 47*4882a593Smuzhiyun #define CLK_CPU_TIMER0 0x520 48*4882a593Smuzhiyun #define CLK_CPU_TIMER1 0x528 49*4882a593Smuzhiyun #define CLK_CPU_SCU 0x530 50*4882a593Smuzhiyun #define CLK_CPU_CREG 0x538 51*4882a593Smuzhiyun #define CLK_CPU_RITIMER 0x600 52*4882a593Smuzhiyun #define CLK_CPU_UART2 0x608 53*4882a593Smuzhiyun #define CLK_CPU_UART3 0x610 54*4882a593Smuzhiyun #define CLK_CPU_TIMER2 0x618 55*4882a593Smuzhiyun #define CLK_CPU_TIMER3 0x620 56*4882a593Smuzhiyun #define CLK_CPU_SSP1 0x628 57*4882a593Smuzhiyun #define CLK_CPU_QEI 0x630 58*4882a593Smuzhiyun #define CLK_PERIPH_BUS 0x700 59*4882a593Smuzhiyun #define CLK_PERIPH_CORE 0x710 60*4882a593Smuzhiyun #define CLK_PERIPH_SGPIO 0x718 61*4882a593Smuzhiyun #define CLK_USB0 0x800 62*4882a593Smuzhiyun #define CLK_USB1 0x900 63*4882a593Smuzhiyun #define CLK_SPI 0xA00 64*4882a593Smuzhiyun #define CLK_ADCHS 0xB00 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Clock Control Unit 2 (CCU2) clock offsets */ 67*4882a593Smuzhiyun #define CLK_AUDIO 0x100 68*4882a593Smuzhiyun #define CLK_APB2_UART3 0x200 69*4882a593Smuzhiyun #define CLK_APB2_UART2 0x300 70*4882a593Smuzhiyun #define CLK_APB0_UART1 0x400 71*4882a593Smuzhiyun #define CLK_APB0_UART0 0x500 72*4882a593Smuzhiyun #define CLK_APB2_SSP1 0x600 73*4882a593Smuzhiyun #define CLK_APB0_SSP0 0x700 74*4882a593Smuzhiyun #define CLK_SDIO 0x800 75