1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 9*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 10*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 11*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12*4882a593Smuzhiyun * following added to such license: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 15*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 16*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 17*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 18*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 19*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 20*4882a593Smuzhiyun * modifications of the software. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this 23*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license 24*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>> 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $ 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _SBPCMCIA_H 33*4882a593Smuzhiyun #define _SBPCMCIA_H 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* All the addresses that are offsets in attribute space are divided 36*4882a593Smuzhiyun * by two to account for the fact that odd bytes are invalid in 37*4882a593Smuzhiyun * attribute space and our read/write routines make the space appear 38*4882a593Smuzhiyun * as if they didn't exist. Still we want to show the original numbers 39*4882a593Smuzhiyun * as documented in the hnd_pcmcia core manual. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* PCMCIA Function Configuration Registers */ 43*4882a593Smuzhiyun #define PCMCIA_FCR (0x700 / 2) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define FCR0_OFF 0 46*4882a593Smuzhiyun #define FCR1_OFF (0x40 / 2) 47*4882a593Smuzhiyun #define FCR2_OFF (0x80 / 2) 48*4882a593Smuzhiyun #define FCR3_OFF (0xc0 / 2) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PCMCIA_FCR0 (0x700 / 2) 51*4882a593Smuzhiyun #define PCMCIA_FCR1 (0x740 / 2) 52*4882a593Smuzhiyun #define PCMCIA_FCR2 (0x780 / 2) 53*4882a593Smuzhiyun #define PCMCIA_FCR3 (0x7c0 / 2) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Standard PCMCIA FCR registers */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define PCMCIA_COR 0 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define COR_RST 0x80 60*4882a593Smuzhiyun #define COR_LEV 0x40 61*4882a593Smuzhiyun #define COR_IRQEN 0x04 62*4882a593Smuzhiyun #define COR_BLREN 0x01 63*4882a593Smuzhiyun #define COR_FUNEN 0x01 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PCICIA_FCSR (2 / 2) 66*4882a593Smuzhiyun #define PCICIA_PRR (4 / 2) 67*4882a593Smuzhiyun #define PCICIA_SCR (6 / 2) 68*4882a593Smuzhiyun #define PCICIA_ESR (8 / 2) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PCM_MEMOFF 0x0000 71*4882a593Smuzhiyun #define F0_MEMOFF 0x1000 72*4882a593Smuzhiyun #define F1_MEMOFF 0x2000 73*4882a593Smuzhiyun #define F2_MEMOFF 0x3000 74*4882a593Smuzhiyun #define F3_MEMOFF 0x4000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Memory base in the function fcr's */ 77*4882a593Smuzhiyun #define MEM_ADDR0 (0x728 / 2) 78*4882a593Smuzhiyun #define MEM_ADDR1 (0x72a / 2) 79*4882a593Smuzhiyun #define MEM_ADDR2 (0x72c / 2) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PCMCIA base plus Srom access in fcr0: */ 82*4882a593Smuzhiyun #define PCMCIA_ADDR0 (0x072e / 2) 83*4882a593Smuzhiyun #define PCMCIA_ADDR1 (0x0730 / 2) 84*4882a593Smuzhiyun #define PCMCIA_ADDR2 (0x0732 / 2) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define MEM_SEG (0x0734 / 2) 87*4882a593Smuzhiyun #define SROM_CS (0x0736 / 2) 88*4882a593Smuzhiyun #define SROM_DATAL (0x0738 / 2) 89*4882a593Smuzhiyun #define SROM_DATAH (0x073a / 2) 90*4882a593Smuzhiyun #define SROM_ADDRL (0x073c / 2) 91*4882a593Smuzhiyun #define SROM_ADDRH (0x073e / 2) 92*4882a593Smuzhiyun #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ 93*4882a593Smuzhiyun #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Values for srom_cs: */ 96*4882a593Smuzhiyun #define SROM_IDLE 0 97*4882a593Smuzhiyun #define SROM_WRITE 1 98*4882a593Smuzhiyun #define SROM_READ 2 99*4882a593Smuzhiyun #define SROM_WEN 4 100*4882a593Smuzhiyun #define SROM_WDS 7 101*4882a593Smuzhiyun #define SROM_DONE 8 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Fields in srom_info: */ 104*4882a593Smuzhiyun #define SRI_SZ_MASK 0x03 105*4882a593Smuzhiyun #define SRI_BLANK 0x04 106*4882a593Smuzhiyun #define SRI_OTP 0x80 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define SROM16K_BANK_SEL_MASK (3 << 11) 109*4882a593Smuzhiyun #define SROM16K_BANK_SHFT_MASK 11 110*4882a593Smuzhiyun #define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1) 111*4882a593Smuzhiyun #define SROM_PRSNT_MASK 0x1 112*4882a593Smuzhiyun #define SROM_SUPPORT_SHIFT_MASK 30 113*4882a593Smuzhiyun #define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK) 114*4882a593Smuzhiyun #define SROM_SIZE_MASK 0x00000006 115*4882a593Smuzhiyun #define SROM_SIZE_2K 2 116*4882a593Smuzhiyun #define SROM_SIZE_512 1 117*4882a593Smuzhiyun #define SROM_SIZE_128 0 118*4882a593Smuzhiyun #define SROM_SIZE_SHFT_MASK 1 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Standard tuples we know about */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define CISTPL_NULL 0x00 123*4882a593Smuzhiyun #define CISTPL_END 0xff /* End of the CIS tuple chain */ 124*4882a593Smuzhiyun #define CISTPL_OFFSET 0xC0 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define CISTPL_BRCM_HNBU 0x80 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define HNBU_BOARDREV 0x02 /* One byte board revision */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */ 135*4882a593Smuzhiyun #define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* sbtmstatelow */ 138*4882a593Smuzhiyun #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ 139*4882a593Smuzhiyun #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* sbtmstatehigh */ 142*4882a593Smuzhiyun #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ 143*4882a593Smuzhiyun #endif /* _SBPCMCIA_H */ 144