Lines Matching +full:0 +full:x700
43 #define PCMCIA_FCR (0x700 / 2)
45 #define FCR0_OFF 0
46 #define FCR1_OFF (0x40 / 2)
47 #define FCR2_OFF (0x80 / 2)
48 #define FCR3_OFF (0xc0 / 2)
50 #define PCMCIA_FCR0 (0x700 / 2)
51 #define PCMCIA_FCR1 (0x740 / 2)
52 #define PCMCIA_FCR2 (0x780 / 2)
53 #define PCMCIA_FCR3 (0x7c0 / 2)
57 #define PCMCIA_COR 0
59 #define COR_RST 0x80
60 #define COR_LEV 0x40
61 #define COR_IRQEN 0x04
62 #define COR_BLREN 0x01
63 #define COR_FUNEN 0x01
70 #define PCM_MEMOFF 0x0000
71 #define F0_MEMOFF 0x1000
72 #define F1_MEMOFF 0x2000
73 #define F2_MEMOFF 0x3000
74 #define F3_MEMOFF 0x4000
77 #define MEM_ADDR0 (0x728 / 2)
78 #define MEM_ADDR1 (0x72a / 2)
79 #define MEM_ADDR2 (0x72c / 2)
82 #define PCMCIA_ADDR0 (0x072e / 2)
83 #define PCMCIA_ADDR1 (0x0730 / 2)
84 #define PCMCIA_ADDR2 (0x0732 / 2)
86 #define MEM_SEG (0x0734 / 2)
87 #define SROM_CS (0x0736 / 2)
88 #define SROM_DATAL (0x0738 / 2)
89 #define SROM_DATAH (0x073a / 2)
90 #define SROM_ADDRL (0x073c / 2)
91 #define SROM_ADDRH (0x073e / 2)
92 #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
93 #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
96 #define SROM_IDLE 0
104 #define SRI_SZ_MASK 0x03
105 #define SRI_BLANK 0x04
106 #define SRI_OTP 0x80
111 #define SROM_PRSNT_MASK 0x1
113 #define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK)
114 #define SROM_SIZE_MASK 0x00000006
117 #define SROM_SIZE_128 0
122 #define CISTPL_NULL 0x00
123 #define CISTPL_END 0xff /* End of the CIS tuple chain */
124 #define CISTPL_OFFSET 0xC0
126 #define CISTPL_BRCM_HNBU 0x80
128 #define HNBU_BOARDREV 0x02 /* One byte board revision */
130 #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
132 #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
134 #define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
135 #define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
138 #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
139 #define SBTML_INT_EN 0x20000 /* enable sb interrupt */
142 #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */