1 /* 2 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $ 30 */ 31 32 #ifndef _SBPCMCIA_H 33 #define _SBPCMCIA_H 34 35 /* All the addresses that are offsets in attribute space are divided 36 * by two to account for the fact that odd bytes are invalid in 37 * attribute space and our read/write routines make the space appear 38 * as if they didn't exist. Still we want to show the original numbers 39 * as documented in the hnd_pcmcia core manual. 40 */ 41 42 /* PCMCIA Function Configuration Registers */ 43 #define PCMCIA_FCR (0x700 / 2) 44 45 #define FCR0_OFF 0 46 #define FCR1_OFF (0x40 / 2) 47 #define FCR2_OFF (0x80 / 2) 48 #define FCR3_OFF (0xc0 / 2) 49 50 #define PCMCIA_FCR0 (0x700 / 2) 51 #define PCMCIA_FCR1 (0x740 / 2) 52 #define PCMCIA_FCR2 (0x780 / 2) 53 #define PCMCIA_FCR3 (0x7c0 / 2) 54 55 /* Standard PCMCIA FCR registers */ 56 57 #define PCMCIA_COR 0 58 59 #define COR_RST 0x80 60 #define COR_LEV 0x40 61 #define COR_IRQEN 0x04 62 #define COR_BLREN 0x01 63 #define COR_FUNEN 0x01 64 65 #define PCICIA_FCSR (2 / 2) 66 #define PCICIA_PRR (4 / 2) 67 #define PCICIA_SCR (6 / 2) 68 #define PCICIA_ESR (8 / 2) 69 70 #define PCM_MEMOFF 0x0000 71 #define F0_MEMOFF 0x1000 72 #define F1_MEMOFF 0x2000 73 #define F2_MEMOFF 0x3000 74 #define F3_MEMOFF 0x4000 75 76 /* Memory base in the function fcr's */ 77 #define MEM_ADDR0 (0x728 / 2) 78 #define MEM_ADDR1 (0x72a / 2) 79 #define MEM_ADDR2 (0x72c / 2) 80 81 /* PCMCIA base plus Srom access in fcr0: */ 82 #define PCMCIA_ADDR0 (0x072e / 2) 83 #define PCMCIA_ADDR1 (0x0730 / 2) 84 #define PCMCIA_ADDR2 (0x0732 / 2) 85 86 #define MEM_SEG (0x0734 / 2) 87 #define SROM_CS (0x0736 / 2) 88 #define SROM_DATAL (0x0738 / 2) 89 #define SROM_DATAH (0x073a / 2) 90 #define SROM_ADDRL (0x073c / 2) 91 #define SROM_ADDRH (0x073e / 2) 92 #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ 93 #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ 94 95 /* Values for srom_cs: */ 96 #define SROM_IDLE 0 97 #define SROM_WRITE 1 98 #define SROM_READ 2 99 #define SROM_WEN 4 100 #define SROM_WDS 7 101 #define SROM_DONE 8 102 103 /* Fields in srom_info: */ 104 #define SRI_SZ_MASK 0x03 105 #define SRI_BLANK 0x04 106 #define SRI_OTP 0x80 107 108 #define SROM16K_BANK_SEL_MASK (3 << 11) 109 #define SROM16K_BANK_SHFT_MASK 11 110 #define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1) 111 #define SROM_PRSNT_MASK 0x1 112 #define SROM_SUPPORT_SHIFT_MASK 30 113 #define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK) 114 #define SROM_SIZE_MASK 0x00000006 115 #define SROM_SIZE_2K 2 116 #define SROM_SIZE_512 1 117 #define SROM_SIZE_128 0 118 #define SROM_SIZE_SHFT_MASK 1 119 120 /* Standard tuples we know about */ 121 122 #define CISTPL_NULL 0x00 123 #define CISTPL_END 0xff /* End of the CIS tuple chain */ 124 #define CISTPL_OFFSET 0xC0 125 126 #define CISTPL_BRCM_HNBU 0x80 127 128 #define HNBU_BOARDREV 0x02 /* One byte board revision */ 129 130 #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ 131 132 #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ 133 134 #define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */ 135 #define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */ 136 137 /* sbtmstatelow */ 138 #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ 139 #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ 140 141 /* sbtmstatehigh */ 142 #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ 143 #endif /* _SBPCMCIA_H */ 144