Searched +full:0 +full:x01f01400 (Results 1 – 12 of 12) sorted by relevance
48 const: 0154 reg = <0x01f01400 0x200>;158 #clock-cells = <0>;167 #clock-cells = <0>;176 #clock-cells = <0>;
46 const: 0111 const: 0169 reg = <0x01f01400 0x200>;173 #clock-cells = <0>;174 clocks = <&rtc 0>, <&osc24M>,182 #clock-cells = <0>;191 #clock-cells = <0>;207 #clock-cells = <0>;209 clocks = <&rtc 0>, <&osc24M>;
130 reg = <0x01c20000 0x400>;140 reg = <0x01f01400 0x100>;
12 #define SUNXI_SRAM_A1_BASE 0x0000000015 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */21 #define SUNXI_DE2_BASE 0x0100000024 #define SUNXI_CPUCFG_BASE 0x0170000027 #define SUNXI_SRAMC_BASE 0x01c0000028 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0>;88 #clock-cells = <0>;95 #clock-cells = <0>;102 #clock-cells = <0>;134 reg = <0x01c0f000 0x1000>;143 #size-cells = <0>;148 reg = <0x01c10000 0x1000>;157 #size-cells = <0>;[all …]
59 simplefb_lcd: framebuffer@0 {63 clocks = <&pll6 0>;81 #size-cells = <0>;83 cpu@0 {86 reg = <0>;102 #clock-cells = <0>;109 #clock-cells = <0>;116 #clock-cells = <0>;118 reg = <0x01c20000 0x4>;125 #clock-cells = <0>;[all …]
64 simplefb_hdmi: framebuffer@0 {68 clocks = <&pll6 0>;76 clocks = <&pll6 0>;94 #size-cells = <0>;96 cpu0: cpu@0 {99 reg = <0>;110 cooling-min-level = <0>;166 reg = <0x40000000 0x80000000>;183 #clock-cells = <0>;188 osc32k: clk@0 {[all …]
90 #size-cells = <0>;92 cpu0: cpu@0 {95 reg = <0>;111 #clock-cells = <0>;119 #clock-cells = <0>;135 reg = <0x01c00000 0x30>;142 reg = <0x01d00000 0x80000>;145 ranges = <0 0x01d00000 0x80000>;147 ve_sram: sram-section@0 {150 reg = <0x000000 0x80000>;[all …]
86 #clock-cells = <0>;94 #clock-cells = <0>;117 reg = <0x01000000 0x10000>;128 compatible = "allwinner,sun8i-h3-de2-mixer-0";129 reg = <0x01100000 0x100000>;138 #size-cells = <0>;152 reg = <0x01c02000 0x1000>;162 reg = <0x01c0c000 0x1000>;171 #size-cells = <0>;173 tcon0_in: port@0 {[all …]
62 #size-cells = <0>;64 cpu0: cpu@0 {71 reg = <0>;115 reg = <0x100>;126 reg = <0x101>;137 reg = <0x102>;148 reg = <0x103>;168 #clock-cells = <0>;181 #clock-cells = <0>;188 #clock-cells = <0>;[all …]
100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;216 #clock-cells = <0>;224 #clock-cells = <0>;241 #clock-cells = <0>;248 #clock-cells = <0>;255 #clock-cells = <0>;257 reg = <0x01c200d0 0x4>;277 reg = <0x01c02000 0x1000>;[all …]
46 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;106 #clock-cells = <0>;113 #clock-cells = <0>;174 polling-delay-passive = <0>;175 polling-delay = <0>;176 thermal-sensors = <&ths 0>;221 polling-delay-passive = <0>;222 polling-delay = <0>;[all …]