1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A31 PRCM Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundeprecated: true 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: allwinner,sun6i-a31-prcm 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunpatternProperties: 23*4882a593Smuzhiyun "^.*_(clk|rst)$": 24*4882a593Smuzhiyun type: object 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun properties: 27*4882a593Smuzhiyun compatible: 28*4882a593Smuzhiyun enum: 29*4882a593Smuzhiyun - allwinner,sun4i-a10-mod0-clk 30*4882a593Smuzhiyun - allwinner,sun6i-a31-apb0-clk 31*4882a593Smuzhiyun - allwinner,sun6i-a31-apb0-gates-clk 32*4882a593Smuzhiyun - allwinner,sun6i-a31-ar100-clk 33*4882a593Smuzhiyun - allwinner,sun6i-a31-clock-reset 34*4882a593Smuzhiyun - fixed-factor-clock 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun allOf: 37*4882a593Smuzhiyun - if: 38*4882a593Smuzhiyun properties: 39*4882a593Smuzhiyun compatible: 40*4882a593Smuzhiyun contains: 41*4882a593Smuzhiyun const: allwinner,sun6i-a31-apb0-clk 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun then: 44*4882a593Smuzhiyun properties: 45*4882a593Smuzhiyun "#clock-cells": 46*4882a593Smuzhiyun const: 0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun # Already checked in the main schema 49*4882a593Smuzhiyun compatible: true 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clocks: 52*4882a593Smuzhiyun maxItems: 1 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clock-output-names: 55*4882a593Smuzhiyun maxItems: 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun phandle: true 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun required: 60*4882a593Smuzhiyun - "#clock-cells" 61*4882a593Smuzhiyun - compatible 62*4882a593Smuzhiyun - clocks 63*4882a593Smuzhiyun - clock-output-names 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun additionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun - if: 68*4882a593Smuzhiyun properties: 69*4882a593Smuzhiyun compatible: 70*4882a593Smuzhiyun contains: 71*4882a593Smuzhiyun const: allwinner,sun6i-a31-apb0-gates-clk 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun then: 74*4882a593Smuzhiyun properties: 75*4882a593Smuzhiyun "#clock-cells": 76*4882a593Smuzhiyun const: 1 77*4882a593Smuzhiyun description: > 78*4882a593Smuzhiyun This additional argument passed to that clock is the 79*4882a593Smuzhiyun offset of the bit controlling this particular gate in 80*4882a593Smuzhiyun the register. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun # Already checked in the main schema 83*4882a593Smuzhiyun compatible: true 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun clocks: 86*4882a593Smuzhiyun maxItems: 1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun clock-output-names: 89*4882a593Smuzhiyun minItems: 1 90*4882a593Smuzhiyun maxItems: 32 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun phandle: true 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun required: 95*4882a593Smuzhiyun - "#clock-cells" 96*4882a593Smuzhiyun - compatible 97*4882a593Smuzhiyun - clocks 98*4882a593Smuzhiyun - clock-output-names 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun additionalProperties: false 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun - if: 103*4882a593Smuzhiyun properties: 104*4882a593Smuzhiyun compatible: 105*4882a593Smuzhiyun contains: 106*4882a593Smuzhiyun const: allwinner,sun6i-a31-ar100-clk 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun then: 109*4882a593Smuzhiyun properties: 110*4882a593Smuzhiyun "#clock-cells": 111*4882a593Smuzhiyun const: 0 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun # Already checked in the main schema 114*4882a593Smuzhiyun compatible: true 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun clocks: 117*4882a593Smuzhiyun maxItems: 4 118*4882a593Smuzhiyun description: > 119*4882a593Smuzhiyun The parent order must match the hardware programming 120*4882a593Smuzhiyun order. 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun clock-output-names: 123*4882a593Smuzhiyun maxItems: 1 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun phandle: true 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun required: 128*4882a593Smuzhiyun - "#clock-cells" 129*4882a593Smuzhiyun - compatible 130*4882a593Smuzhiyun - clocks 131*4882a593Smuzhiyun - clock-output-names 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun additionalProperties: false 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun - if: 136*4882a593Smuzhiyun properties: 137*4882a593Smuzhiyun compatible: 138*4882a593Smuzhiyun contains: 139*4882a593Smuzhiyun const: allwinner,sun6i-a31-clock-reset 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun then: 142*4882a593Smuzhiyun properties: 143*4882a593Smuzhiyun "#reset-cells": 144*4882a593Smuzhiyun const: 1 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun # Already checked in the main schema 147*4882a593Smuzhiyun compatible: true 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun phandle: true 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun required: 152*4882a593Smuzhiyun - "#reset-cells" 153*4882a593Smuzhiyun - compatible 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun additionalProperties: false 156*4882a593Smuzhiyun 157*4882a593Smuzhiyunrequired: 158*4882a593Smuzhiyun - compatible 159*4882a593Smuzhiyun - reg 160*4882a593Smuzhiyun 161*4882a593SmuzhiyunadditionalProperties: false 162*4882a593Smuzhiyun 163*4882a593Smuzhiyunexamples: 164*4882a593Smuzhiyun - | 165*4882a593Smuzhiyun #include <dt-bindings/clock/sun6i-a31-ccu.h> 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun prcm@1f01400 { 168*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-prcm"; 169*4882a593Smuzhiyun reg = <0x01f01400 0x200>; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun ar100: ar100_clk { 172*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-ar100-clk"; 173*4882a593Smuzhiyun #clock-cells = <0>; 174*4882a593Smuzhiyun clocks = <&rtc 0>, <&osc24M>, 175*4882a593Smuzhiyun <&ccu CLK_PLL_PERIPH>, 176*4882a593Smuzhiyun <&ccu CLK_PLL_PERIPH>; 177*4882a593Smuzhiyun clock-output-names = "ar100"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun ahb0: ahb0_clk { 181*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 182*4882a593Smuzhiyun #clock-cells = <0>; 183*4882a593Smuzhiyun clock-div = <1>; 184*4882a593Smuzhiyun clock-mult = <1>; 185*4882a593Smuzhiyun clocks = <&ar100>; 186*4882a593Smuzhiyun clock-output-names = "ahb0"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun apb0: apb0_clk { 190*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-apb0-clk"; 191*4882a593Smuzhiyun #clock-cells = <0>; 192*4882a593Smuzhiyun clocks = <&ahb0>; 193*4882a593Smuzhiyun clock-output-names = "apb0"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun apb0_gates: apb0_gates_clk { 197*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 198*4882a593Smuzhiyun #clock-cells = <1>; 199*4882a593Smuzhiyun clocks = <&apb0>; 200*4882a593Smuzhiyun clock-output-names = "apb0_pio", "apb0_ir", 201*4882a593Smuzhiyun "apb0_timer", "apb0_p2wi", 202*4882a593Smuzhiyun "apb0_uart", "apb0_1wire", 203*4882a593Smuzhiyun "apb0_i2c"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun ir_clk: ir_clk { 207*4882a593Smuzhiyun #clock-cells = <0>; 208*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-mod0-clk"; 209*4882a593Smuzhiyun clocks = <&rtc 0>, <&osc24M>; 210*4882a593Smuzhiyun clock-output-names = "ir"; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun apb0_rst: apb0_rst { 214*4882a593Smuzhiyun compatible = "allwinner,sun6i-a31-clock-reset"; 215*4882a593Smuzhiyun #reset-cells = <1>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun... 220