xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/allwinner,sun8i-a23-prcm.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A23 PRCM Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunproperties:
16*4882a593Smuzhiyun  compatible:
17*4882a593Smuzhiyun    const: allwinner,sun8i-a23-prcm
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  reg:
20*4882a593Smuzhiyun    maxItems: 1
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunpatternProperties:
23*4882a593Smuzhiyun  "^.*(clk|rst|codec).*$":
24*4882a593Smuzhiyun    type: object
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun    properties:
27*4882a593Smuzhiyun      compatible:
28*4882a593Smuzhiyun        enum:
29*4882a593Smuzhiyun          - fixed-factor-clock
30*4882a593Smuzhiyun          - allwinner,sun8i-a23-apb0-clk
31*4882a593Smuzhiyun          - allwinner,sun8i-a23-apb0-gates-clk
32*4882a593Smuzhiyun          - allwinner,sun6i-a31-clock-reset
33*4882a593Smuzhiyun          - allwinner,sun8i-a23-codec-analog
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun    required:
36*4882a593Smuzhiyun      - compatible
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun    allOf:
39*4882a593Smuzhiyun      - if:
40*4882a593Smuzhiyun          properties:
41*4882a593Smuzhiyun            compatible:
42*4882a593Smuzhiyun              contains:
43*4882a593Smuzhiyun                const: allwinner,sun8i-a23-apb0-clk
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun        then:
46*4882a593Smuzhiyun          properties:
47*4882a593Smuzhiyun            "#clock-cells":
48*4882a593Smuzhiyun              const: 0
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun            # Already checked in the main schema
51*4882a593Smuzhiyun            compatible: true
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun            clocks:
54*4882a593Smuzhiyun              maxItems: 1
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun            clock-output-names:
57*4882a593Smuzhiyun              maxItems: 1
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun            phandle: true
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun          required:
62*4882a593Smuzhiyun            - "#clock-cells"
63*4882a593Smuzhiyun            - compatible
64*4882a593Smuzhiyun            - clocks
65*4882a593Smuzhiyun            - clock-output-names
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun          additionalProperties: false
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun      - if:
70*4882a593Smuzhiyun          properties:
71*4882a593Smuzhiyun            compatible:
72*4882a593Smuzhiyun              contains:
73*4882a593Smuzhiyun                const: allwinner,sun8i-a23-apb0-gates-clk
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun        then:
76*4882a593Smuzhiyun          properties:
77*4882a593Smuzhiyun            "#clock-cells":
78*4882a593Smuzhiyun              const: 1
79*4882a593Smuzhiyun              description: >
80*4882a593Smuzhiyun                This additional argument passed to that clock is the
81*4882a593Smuzhiyun                offset of the bit controlling this particular gate in
82*4882a593Smuzhiyun                the register.
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun            # Already checked in the main schema
85*4882a593Smuzhiyun            compatible: true
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun            clocks:
88*4882a593Smuzhiyun              maxItems: 1
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun            clock-output-names:
91*4882a593Smuzhiyun              minItems: 1
92*4882a593Smuzhiyun              maxItems: 32
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun            phandle: true
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun          required:
97*4882a593Smuzhiyun            - "#clock-cells"
98*4882a593Smuzhiyun            - compatible
99*4882a593Smuzhiyun            - clocks
100*4882a593Smuzhiyun            - clock-output-names
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun          additionalProperties: false
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun      - if:
105*4882a593Smuzhiyun          properties:
106*4882a593Smuzhiyun            compatible:
107*4882a593Smuzhiyun              contains:
108*4882a593Smuzhiyun                const: allwinner,sun6i-a31-clock-reset
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun        then:
111*4882a593Smuzhiyun          properties:
112*4882a593Smuzhiyun            "#reset-cells":
113*4882a593Smuzhiyun              const: 1
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun            # Already checked in the main schema
116*4882a593Smuzhiyun            compatible: true
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun            phandle: true
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun          required:
121*4882a593Smuzhiyun            - "#reset-cells"
122*4882a593Smuzhiyun            - compatible
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun          additionalProperties: false
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun      - if:
127*4882a593Smuzhiyun          properties:
128*4882a593Smuzhiyun            compatible:
129*4882a593Smuzhiyun              contains:
130*4882a593Smuzhiyun                const: allwinner,sun8i-a23-codec-analog
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun        then:
133*4882a593Smuzhiyun          properties:
134*4882a593Smuzhiyun            # Already checked in the main schema
135*4882a593Smuzhiyun            compatible: true
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun            phandle: true
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun          required:
140*4882a593Smuzhiyun            - compatible
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun          additionalProperties: false
143*4882a593Smuzhiyun
144*4882a593Smuzhiyunrequired:
145*4882a593Smuzhiyun  - compatible
146*4882a593Smuzhiyun  - reg
147*4882a593Smuzhiyun
148*4882a593SmuzhiyunadditionalProperties: false
149*4882a593Smuzhiyun
150*4882a593Smuzhiyunexamples:
151*4882a593Smuzhiyun  - |
152*4882a593Smuzhiyun    prcm@1f01400 {
153*4882a593Smuzhiyun        compatible = "allwinner,sun8i-a23-prcm";
154*4882a593Smuzhiyun        reg = <0x01f01400 0x200>;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun        ar100: ar100_clk {
157*4882a593Smuzhiyun            compatible = "fixed-factor-clock";
158*4882a593Smuzhiyun            #clock-cells = <0>;
159*4882a593Smuzhiyun            clock-div = <1>;
160*4882a593Smuzhiyun            clock-mult = <1>;
161*4882a593Smuzhiyun            clocks = <&osc24M>;
162*4882a593Smuzhiyun            clock-output-names = "ar100";
163*4882a593Smuzhiyun        };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun        ahb0: ahb0_clk {
166*4882a593Smuzhiyun            compatible = "fixed-factor-clock";
167*4882a593Smuzhiyun            #clock-cells = <0>;
168*4882a593Smuzhiyun            clock-div = <1>;
169*4882a593Smuzhiyun            clock-mult = <1>;
170*4882a593Smuzhiyun            clocks = <&ar100>;
171*4882a593Smuzhiyun            clock-output-names = "ahb0";
172*4882a593Smuzhiyun        };
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun        apb0: apb0_clk {
175*4882a593Smuzhiyun            compatible = "allwinner,sun8i-a23-apb0-clk";
176*4882a593Smuzhiyun            #clock-cells = <0>;
177*4882a593Smuzhiyun            clocks = <&ahb0>;
178*4882a593Smuzhiyun            clock-output-names = "apb0";
179*4882a593Smuzhiyun        };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun        apb0_gates: apb0_gates_clk {
182*4882a593Smuzhiyun            compatible = "allwinner,sun8i-a23-apb0-gates-clk";
183*4882a593Smuzhiyun            #clock-cells = <1>;
184*4882a593Smuzhiyun            clocks = <&apb0>;
185*4882a593Smuzhiyun            clock-output-names = "apb0_pio", "apb0_timer",
186*4882a593Smuzhiyun                                 "apb0_rsb", "apb0_uart",
187*4882a593Smuzhiyun                                 "apb0_i2c";
188*4882a593Smuzhiyun        };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun        apb0_rst: apb0_rst {
191*4882a593Smuzhiyun            compatible = "allwinner,sun6i-a31-clock-reset";
192*4882a593Smuzhiyun            #reset-cells = <1>;
193*4882a593Smuzhiyun        };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun        codec_analog: codec-analog {
196*4882a593Smuzhiyun            compatible = "allwinner,sun8i-a23-codec-analog";
197*4882a593Smuzhiyun        };
198*4882a593Smuzhiyun    };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun...
201