Lines Matching +full:0 +full:x01f01400
56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
88 #clock-cells = <0>;
95 #clock-cells = <0>;
102 #clock-cells = <0>;
134 reg = <0x01c0f000 0x1000>;
143 #size-cells = <0>;
148 reg = <0x01c10000 0x1000>;
157 #size-cells = <0>;
162 reg = <0x01c11000 0x1000>;
171 #size-cells = <0>;
176 reg = <0x01c19000 0x0400>;
181 phys = <&usbphy 0>;
183 extcon = <&usbphy 0>;
189 reg = <0x01c19400 0x14>,
190 <0x01c1a800 0x4>,
191 <0x01c1b800 0x4>;
209 reg = <0x01c1a000 0x100>;
221 reg = <0x01c1a400 0x100>;
231 reg = <0x01c1b000 0x100>;
245 reg = <0x01c1b400 0x100>;
257 reg = <0x01c20000 0x400>;
266 reg = <0x01c20800 0x400>;
306 uart0_pins_a: uart0@0 {
324 reg = <0x01c28000 0x400>;
325 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
335 reg = <0x01c28400 0x400>;
346 reg = <0x01c28800 0x400>;
357 reg = <0x01c28c00 0x400>;
368 reg = <0x01c29000 0x400>;
379 reg = <0x01c2ac00 0x400>;
385 #size-cells = <0>;
390 reg = <0x01c2b000 0x400>;
396 #size-cells = <0>;
401 reg = <0x01c2b400 0x400>;
407 #size-cells = <0>;
412 reg = <0x01c81000 0x1000>,
413 <0x01c82000 0x2000>,
414 <0x01c84000 0x2000>,
415 <0x01c86000 0x2000>;
423 reg = <0x01f00000 0x54>;
430 reg = <0x01f01400 0x100>;
439 reg = <0x01f02c00 0x400>;