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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dpci.c51 hose = &pci_hose[0]; in pci_mpc85xx_init()
53 hose->first_busno = 0; in pci_mpc85xx_init()
54 hose->last_busno = 0xff; in pci_mpc85xx_init()
57 (CONFIG_SYS_IMMR+0x8000), in pci_mpc85xx_init()
58 (CONFIG_SYS_IMMR+0x8004)); in pci_mpc85xx_init()
63 dev = PCI_BDF(hose->first_busno, 0, 0); in pci_mpc85xx_init()
71 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); in pci_mpc85xx_init()
83 pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff; in pci_mpc85xx_init()
84 pcix->potear1 = 0x00000000; in pci_mpc85xx_init()
85 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; in pci_mpc85xx_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-pro4.c31 tmp |= 0x00000001; in vpll_init()
34 tmp |= 0x00000001; in vpll_init()
39 tmp &= ~0x10000000; in vpll_init()
42 tmp &= ~0x10000000; in vpll_init()
45 /* Set VPLA_M and VPLB_M to 0x20 */ in vpll_init()
47 tmp &= ~0x0000007f; in vpll_init()
48 tmp |= 0x00000020; in vpll_init()
51 tmp &= ~0x0000007f; in vpll_init()
52 tmp |= 0x00000020; in vpll_init()
59 tmp &= ~0x000fffff; in vpll_init()
[all …]
H A Dpll-ld4.c24 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ in upll_init()
26 tmp &= ~0x18000000; in upll_init()
33 tmp &= ~0x07ffffff; in upll_init()
34 tmp |= 0x0228f5c0; in upll_init()
37 tmp &= ~0x07ffffff; in upll_init()
38 tmp |= 0x02328000; in upll_init()
45 tmp |= 0x08000000; in upll_init()
52 tmp |= 0x10000000; in upll_init()
65 tmp |= 0x00000001; in vpll_init()
68 tmp |= 0x00000001; in vpll_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
H A Dgc_9_0_default.h26 #define mmGRBM_CNTL_DEFAULT 0x00000018
27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
28 #define mmGRBM_STATUS2_DEFAULT 0x00000000
29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
30 #define mmGRBM_STATUS_DEFAULT 0x00000000
31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_tssi_8852b.c28 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _tssi_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _tssi_reload_bb_registers_8852b()
67 channelIndex = 0; in _halrf_ch_to_idx()
76 if (idx >= 0 && idx <= 13) in _halrf_idx_to_ch()
78 else if (idx >= (0 + 14) && idx <= (14 + 14)) in _halrf_idx_to_ch()
85 channelIndex = 0; in _halrf_idx_to_ch()
94 struct rf_pmac_tx_info tx_info = {0}; in _halrf_tssi_hw_tx_8852b()
103 tx_info.txagc_cw = 0; in _halrf_tssi_hw_tx_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_tssi_8852b.c28 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Backup BB 0x%x = 0x%x\n", in _tssi_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_TX_PWR_TRACK, "[TSSI] Reload BB 0x%x = 0x%x\n", in _tssi_reload_bb_registers_8852b()
67 channelIndex = 0; in _halrf_ch_to_idx()
76 if (idx >= 0 && idx <= 13) in _halrf_idx_to_ch()
78 else if (idx >= (0 + 14) && idx <= (14 + 14)) in _halrf_idx_to_ch()
85 channelIndex = 0; in _halrf_idx_to_ch()
94 struct rf_pmac_tx_info tx_info = {0}; in _halrf_tssi_hw_tx_8852b()
103 tx_info.txagc_cw = 0; in _halrf_tssi_hw_tx_8852b()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Duvd_v3_1.c46 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit()
47 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
49 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v3_1_semaphore_emit()
52 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v3_1_semaphore_emit()
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
H A Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit()
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit()
52 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
55 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
57 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/ti-vpe/
H A Dvpe_regs.h16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
/OK3568_Linux_fs/kernel/drivers/hwtracing/coresight/
H A Dcoresight-priv.h16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
20 #define CORESIGHT_ITCTRL 0xf00
21 #define CORESIGHT_CLAIMSET 0xfa0
22 #define CORESIGHT_CLAIMCLR 0xfa4
23 #define CORESIGHT_LAR 0xfb0
24 #define CORESIGHT_LSR 0xfb4
25 #define CORESIGHT_DEVARCH 0xfbc
26 #define CORESIGHT_AUTHSTATUS 0xfb8
27 #define CORESIGHT_DEVID 0xfc8
[all …]
H A Dcoresight-tpiu.c22 #define TPIU_SUPP_PORTSZ 0x000
23 #define TPIU_CURR_PORTSZ 0x004
24 #define TPIU_SUPP_TRIGMODES 0x100
25 #define TPIU_TRIG_CNTRVAL 0x104
26 #define TPIU_TRIG_MULT 0x108
27 #define TPIU_SUPP_TESTPATM 0x200
28 #define TPIU_CURR_TESTPATM 0x204
29 #define TPIU_TEST_PATREPCNTR 0x208
30 #define TPIU_FFSR 0x300
31 #define TPIU_FFCR 0x304
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/spirit/home/support/detail/math/detail/
H A Dfp_traits.hpp113 BOOST_STATIC_CONSTANT(uint32_t, sign = 0x80000000);
158 // sign bit = 0 in do_init_()
159 // exponent: first and last bit = 0, all other bits = 1 in do_init_()
161 // mantissa: first bit = 1, all other bits = 0 in do_init_()
165 for(size_t k = 0; k <= sizeof(T) - 4; ++k) { in do_init_()
171 case 0x3f400000: // IEEE single precision format in do_init_()
174 exponent = 0x7f800000; in do_init_()
175 flag = 0x00000000; in do_init_()
176 mantissa = 0x007fffff; in do_init_()
179 case 0x3fe80000: // IEEE double precision format in do_init_()
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dmpc8349_pci.h5 #define M8265_PCIBR0 0x101ac
6 #define M8265_PCIBR1 0x101b0
7 #define M8265_PCIMSK0 0x101c4
8 #define M8265_PCIMSK1 0x101c8
12 #define PCIBR_ENABLE 0x00000001
16 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
17 #define PCIMSK_64KB 0xFFFF0000
18 #define PCIMSK_128KB 0xFFFE0000
19 #define PCIMSK_256KB 0xFFFC0000
20 #define PCIMSK_512KB 0xFFF80000
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/math/special_functions/detail/
H A Dfp_traits.hpp37 #define FP_ZERO 0
51 && (_GLIBCXX_USE_C99_FP_MACROS_DYNAMIC != 0))
53 # if _STLPORT_VERSION >= 0x520
181 BOOST_STATIC_CONSTANT(uint32_t, sign = 0x80000000u);
182 BOOST_STATIC_CONSTANT(uint32_t, exponent = 0x7f800000);
183 BOOST_STATIC_CONSTANT(uint32_t, flag = 0x00000000);
184 BOOST_STATIC_CONSTANT(uint32_t, significand = 0x007fffff);
200 BOOST_STATIC_CONSTANT(uint32_t, sign = 0x80000000u);
201 BOOST_STATIC_CONSTANT(uint32_t, exponent = 0x7ff00000);
202 BOOST_STATIC_CONSTANT(uint32_t, flag = 0);
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath11k/
H A Dhal.h34 #define HAL_SHADOW_BASE_ADDR 0x000008fc
42 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
43 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
44 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000
45 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000
46 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000
47 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000
48 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
51 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
52 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igc/
H A Digc_diag.c8 { IGC_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9 { IGC_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
10 { IGC_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
11 { IGC_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
12 { IGC_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
13 { IGC_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
14 { IGC_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
15 { IGC_FCRTH, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
16 { IGC_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
17 { IGC_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/OK3568_Linux_fs/u-boot/board/ti/am43xx/
H A Dboard.c118 0x00500050,
119 0x00350035,
120 0x00350035,
121 0x00350035,
122 0x00350035,
123 0x00350035,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/carl9170/
H A Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pit.h17 u32 mr; /* 0x00 Mode Register */
18 u32 sr; /* 0x04 Status Register */
19 u32 pivr; /* 0x08 Periodic Interval Value Register */
20 u32 piir; /* 0x0C Periodic Interval Image Register */
23 #define AT91_PIT_MR_IEN 0x02000000
24 #define AT91_PIT_MR_EN 0x01000000
25 #define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dregs.h5 #define NV04_PGRAPH_DEBUG_0 0x00400080
6 #define NV04_PGRAPH_DEBUG_1 0x00400084
7 #define NV04_PGRAPH_DEBUG_2 0x00400088
8 #define NV04_PGRAPH_DEBUG_3 0x0040008c
9 #define NV10_PGRAPH_DEBUG_4 0x00400090
10 #define NV03_PGRAPH_INTR 0x00400100
11 #define NV03_PGRAPH_NSTATUS 0x00400104
20 #define NV03_PGRAPH_NSOURCE 0x00400108
21 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0)
40 #define NV03_PGRAPH_INTR_EN 0x00400140
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/
H A Dpci-nanoengine.c22 if (bus->number != 0 || (devfn >> 3) != 0) in nanoengine_pci_map_bus()
42 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
62 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
63 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
64 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
65 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
66 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
71 pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
72 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
73 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
[all …]

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