118 	0x00500050,
119 	0x00350035,
120 	0x00350035,
121 	0x00350035,
122 	0x00350035,
123 	0x00350035,
124 	0x00000000,
125 	0x00000000,
126 	0x00000000,
127 	0x00000000,
128 	0x00000000,
129 	0x00000000,
130 	0x00000000,
131 	0x00000000,
132 	0x00000000,
133 	0x00000000,
134 	0x00000000,
135 	0x00000000,
136 	0x40001000,
137 	0x08102040
148 	.emif_sdram_config_ext	= 0x1,
152 	.sdram_config			= 0x808012BA,
153 	.ref_ctrl			= 0x0000040D,
154 	.sdram_tim1			= 0xEA86B411,
155 	.sdram_tim2			= 0x103A094A,
156 	.sdram_tim3			= 0x0F6BA37F,
157 	.read_idle_ctrl			= 0x00050000,
158 	.zq_config			= 0x50074BE4,
159 	.temp_alert_config		= 0x0,
160 	.emif_rd_wr_lvl_rmp_win		= 0x0,
161 	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
162 	.emif_rd_wr_lvl_ctl		= 0x0,
163 	.emif_ddr_phy_ctlr_1		= 0x0E284006,
164 	.emif_rd_wr_exec_thresh		= 0x80000405,
165 	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
166 	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
167 	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
168 	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
169 	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
170 	.emif_prio_class_serv_map	= 0x80000001,
171 	.emif_connect_id_serv_1_map	= 0x80000094,
172 	.emif_connect_id_serv_2_map	= 0x00000000,
173 	.emif_cos_config			= 0x000FFFFF
184 	.emif_sdram_config_ext	= 0xc163,
188 	.sdram_config			= 0x638413B2,
189 	.ref_ctrl			= 0x00000C30,
190 	.sdram_tim1			= 0xEAAAD4DB,
191 	.sdram_tim2			= 0x266B7FDA,
192 	.sdram_tim3			= 0x107F8678,
193 	.read_idle_ctrl			= 0x00050000,
194 	.zq_config			= 0x50074BE4,
195 	.temp_alert_config		= 0x0,
196 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
197 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
198 	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
199 	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
200 	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
201 	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
202 	.emif_rd_wr_lvl_rmp_win		= 0x0,
203 	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
204 	.emif_rd_wr_lvl_ctl		= 0x0,
205 	.emif_rd_wr_exec_thresh		= 0x80000405,
206 	.emif_prio_class_serv_map	= 0x80000001,
207 	.emif_connect_id_serv_1_map	= 0x80000094,
208 	.emif_connect_id_serv_2_map	= 0x00000000,
209 	.emif_cos_config		= 0x000FFFFF
214 	.sdram_config			= 0x638413B2,
215 	.ref_ctrl			= 0x00000C30,
216 	.sdram_tim1			= 0xEAAAD4DB,
217 	.sdram_tim2			= 0x266B7FDA,
218 	.sdram_tim3			= 0x107F8678,
219 	.read_idle_ctrl			= 0x00050000,
220 	.zq_config			= 0x50074BE4,
221 	.temp_alert_config		= 0x0,
222 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
223 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
224 	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
225 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
226 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
227 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
228 	.emif_rd_wr_exec_thresh		= 0x80000405,
229 	.emif_prio_class_serv_map	= 0x80000001,
230 	.emif_connect_id_serv_1_map	= 0x80000094,
231 	.emif_connect_id_serv_2_map	= 0x00000000,
232 	.emif_cos_config		= 0x000FFFFF
237 	.sdram_config			= 0x638413B2,
238 	.ref_ctrl			= 0x00000C30,
239 	.sdram_tim1			= 0xEAAAD4DB,
240 	.sdram_tim2			= 0x266B7FDA,
241 	.sdram_tim3			= 0x107F8678,
242 	.read_idle_ctrl			= 0x00050000,
243 	.zq_config			= 0x50074BE4,
244 	.temp_alert_config		= 0x0,
245 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
246 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
247 	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
248 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
249 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
250 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
251 	.emif_rd_wr_exec_thresh		= 0x80000405,
252 	.emif_prio_class_serv_map	= 0x80000001,
253 	.emif_connect_id_serv_1_map	= 0x80000094,
254 	.emif_connect_id_serv_2_map	= 0x00000000,
255 	.emif_cos_config		= 0x000FFFFF
259 	.sdram_config			= 0x638413b2,
260 	.sdram_config2			= 0x00000000,
261 	.ref_ctrl			= 0x00000c30,
262 	.sdram_tim1			= 0xeaaad4db,
263 	.sdram_tim2			= 0x266b7fda,
264 	.sdram_tim3			= 0x107f8678,
265 	.read_idle_ctrl			= 0x00050000,
266 	.zq_config			= 0x50074be4,
267 	.temp_alert_config		= 0x0,
268 	.emif_ddr_phy_ctlr_1		= 0x0e084008,
269 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
270 	.emif_ddr_ext_phy_ctrl_2	= 0x89,
271 	.emif_ddr_ext_phy_ctrl_3	= 0x90,
272 	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
273 	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
274 	.emif_rd_wr_lvl_rmp_win		= 0x0,
275 	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
276 	.emif_rd_wr_lvl_ctl		= 0x00000000,
277 	.emif_rd_wr_exec_thresh		= 0x80000000,
278 	.emif_prio_class_serv_map	= 0x80000001,
279 	.emif_connect_id_serv_1_map	= 0x80000094,
280 	.emif_connect_id_serv_2_map	= 0x00000000,
281 	.emif_cos_config		= 0x000FFFFF
285 	.sdram_config			= 0x61a11b32,
286 	.sdram_config2			= 0x00000000,
287 	.ref_ctrl			= 0x00000c30,
288 	.sdram_tim1			= 0xeaaad4db,
289 	.sdram_tim2			= 0x266b7fda,
290 	.sdram_tim3			= 0x107f8678,
291 	.read_idle_ctrl			= 0x00050000,
292 	.zq_config			= 0x50074be4,
293 	.temp_alert_config		= 0x00000000,
294 	.emif_ddr_phy_ctlr_1		= 0x00008009,
295 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
296 	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
297 	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
298 	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
299 	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
300 	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
301 	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
302 	.emif_rd_wr_lvl_ctl		= 0x00000000,
303 	.emif_rd_wr_exec_thresh		= 0x00000405,
304 	.emif_prio_class_serv_map	= 0x00000000,
305 	.emif_connect_id_serv_1_map	= 0x00000000,
306 	.emif_connect_id_serv_2_map	= 0x00000000,
307 	.emif_cos_config		= 0x00ffffff
342  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
344  * bit with rightmost '0'.
351 	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */  in get_opp_offset()
352 	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;  in get_opp_offset()
531 		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);  in sdram_init()
534 		config_ddr(0, &ioregs_ddr3, NULL, NULL,  in sdram_init()
535 			   &ddr3_emif_regs_400Mhz_production, 0);  in sdram_init()
538 		config_ddr(0, &ioregs_ddr3, NULL, NULL,  in sdram_init()
539 			   &ddr3_emif_regs_400Mhz_beta, 0);  in sdram_init()
542 		config_ddr(0, &ioregs_ddr3, NULL, NULL,  in sdram_init()
543 			   &ddr3_emif_regs_400Mhz, 0);  in sdram_init()
546 			   &ddr3_sk_emif_regs_400Mhz, 0);  in sdram_init()
549 			   &ddr3_idk_emif_regs_400Mhz, 0);  in sdram_init()
571 	return 0;  in power_init_board()
580 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;  in board_init()
599 	mreqprio_0 |= 0x77;  in board_init()
605 	modena_init0_bw_fractional |= 0x10;  in board_init()
606 	modena_init0_bw_integer |= 0x3;  in board_init()
615 	return 0;  in board_init()
631 	return 0;  in board_late_init()
640 	.index = 0,
646 	.index = 0,
651 	.index = 0,
680 	return 0;  in usb_gadget_handle_interrupts()
690 	case 0:  in board_usb_init()
713 	return 0;  in board_usb_init()
720 	case 0:  in board_usb_cleanup()
734 	return 0;  in board_usb_cleanup()
748 		.slave_reg_ofs	= 0x208,
749 		.sliver_reg_ofs	= 0xd80,
753 		.slave_reg_ofs	= 0x308,
754 		.sliver_reg_ofs	= 0xdc0,
762 	.mdio_div		= 0xff,
764 	.cpdma_reg_ofs		= 0x800,
767 	.ale_reg_ofs		= 0xd00,
769 	.host_port_reg_ofs	= 0x108,
770 	.hw_stats_reg_ofs	= 0x900,
771 	.bd_ram_ofs		= 0x2000,
774 	.host_port_num		= 0,
787 	mac_addr[0] = mac_hi & 0xFF;  in board_eth_init()
788 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;  in board_eth_init()
789 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;  in board_eth_init()
790 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;  in board_eth_init()
791 	mac_addr[4] = mac_lo & 0xFF;  in board_eth_init()
792 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;  in board_eth_init()
802 	mac_addr[0] = mac_hi & 0xFF;  in board_eth_init()
803 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;  in board_eth_init()
804 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;  in board_eth_init()
805 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;  in board_eth_init()
806 	mac_addr[4] = mac_lo & 0xFF;  in board_eth_init()
807 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;  in board_eth_init()
816 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;  in board_eth_init()
817 		cpsw_slaves[0].phy_addr = 16;  in board_eth_init()
820 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;  in board_eth_init()
821 		cpsw_slaves[0].phy_addr = 4;  in board_eth_init()
825 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;  in board_eth_init()
826 		cpsw_slaves[0].phy_addr = 0;  in board_eth_init()
829 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;  in board_eth_init()
830 		cpsw_slaves[0].phy_addr = 0;  in board_eth_init()
834 	if (rv < 0)  in board_eth_init()
846 	return 0;  in ft_board_setup()
854 		return 0;  in board_fit_config_name_match()
856 		return 0;  in board_fit_config_name_match()
858 		return 0;  in board_fit_config_name_match()
860 		return 0;  in board_fit_config_name_match()