1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc. 4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 14*4882a593Smuzhiyun * all copies or substantial portions of the Software. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Authors: Dave Airlie 25*4882a593Smuzhiyun * Alex Deucher 26*4882a593Smuzhiyun * Jerome Glisse 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #ifndef __R600_REG_H__ 29*4882a593Smuzhiyun #define __R600_REG_H__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define R600_PCIE_PORT_INDEX 0x0038 32*4882a593Smuzhiyun #define R600_PCIE_PORT_DATA 0x003c 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define R600_RCU_INDEX 0x0100 35*4882a593Smuzhiyun #define R600_RCU_DATA 0x0104 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define R600_UVD_CTX_INDEX 0xf4a0 38*4882a593Smuzhiyun #define R600_UVD_CTX_DATA 0xf4a4 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define R600_MC_VM_FB_LOCATION 0x2180 41*4882a593Smuzhiyun #define R600_MC_FB_BASE_MASK 0x0000FFFF 42*4882a593Smuzhiyun #define R600_MC_FB_BASE_SHIFT 0 43*4882a593Smuzhiyun #define R600_MC_FB_TOP_MASK 0xFFFF0000 44*4882a593Smuzhiyun #define R600_MC_FB_TOP_SHIFT 16 45*4882a593Smuzhiyun #define R600_MC_VM_AGP_TOP 0x2184 46*4882a593Smuzhiyun #define R600_MC_AGP_TOP_MASK 0x0003FFFF 47*4882a593Smuzhiyun #define R600_MC_AGP_TOP_SHIFT 0 48*4882a593Smuzhiyun #define R600_MC_VM_AGP_BOT 0x2188 49*4882a593Smuzhiyun #define R600_MC_AGP_BOT_MASK 0x0003FFFF 50*4882a593Smuzhiyun #define R600_MC_AGP_BOT_SHIFT 0 51*4882a593Smuzhiyun #define R600_MC_VM_AGP_BASE 0x218c 52*4882a593Smuzhiyun #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 53*4882a593Smuzhiyun #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 54*4882a593Smuzhiyun #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 55*4882a593Smuzhiyun #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 56*4882a593Smuzhiyun #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define R700_MC_VM_FB_LOCATION 0x2024 59*4882a593Smuzhiyun #define R700_MC_FB_BASE_MASK 0x0000FFFF 60*4882a593Smuzhiyun #define R700_MC_FB_BASE_SHIFT 0 61*4882a593Smuzhiyun #define R700_MC_FB_TOP_MASK 0xFFFF0000 62*4882a593Smuzhiyun #define R700_MC_FB_TOP_SHIFT 16 63*4882a593Smuzhiyun #define R700_MC_VM_AGP_TOP 0x2028 64*4882a593Smuzhiyun #define R700_MC_AGP_TOP_MASK 0x0003FFFF 65*4882a593Smuzhiyun #define R700_MC_AGP_TOP_SHIFT 0 66*4882a593Smuzhiyun #define R700_MC_VM_AGP_BOT 0x202c 67*4882a593Smuzhiyun #define R700_MC_AGP_BOT_MASK 0x0003FFFF 68*4882a593Smuzhiyun #define R700_MC_AGP_BOT_SHIFT 0 69*4882a593Smuzhiyun #define R700_MC_VM_AGP_BASE 0x2030 70*4882a593Smuzhiyun #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 71*4882a593Smuzhiyun #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 72*4882a593Smuzhiyun #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 73*4882a593Smuzhiyun #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 74*4882a593Smuzhiyun #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define R600_RAMCFG 0x2408 77*4882a593Smuzhiyun # define R600_CHANSIZE (1 << 7) 78*4882a593Smuzhiyun # define R600_CHANSIZE_OVERRIDE (1 << 10) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define R600_GENERAL_PWRMGT 0x618 82*4882a593Smuzhiyun # define R600_OPEN_DRAIN_PADS (1 << 11) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define R600_LOWER_GPIO_ENABLE 0x710 85*4882a593Smuzhiyun #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 86*4882a593Smuzhiyun #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c 87*4882a593Smuzhiyun #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 88*4882a593Smuzhiyun #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define R600_D1GRPH_SWAP_CONTROL 0x610C 91*4882a593Smuzhiyun # define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 92*4882a593Smuzhiyun # define R600_D1GRPH_SWAP_ENDIAN_NONE 0 93*4882a593Smuzhiyun # define R600_D1GRPH_SWAP_ENDIAN_16BIT 1 94*4882a593Smuzhiyun # define R600_D1GRPH_SWAP_ENDIAN_32BIT 2 95*4882a593Smuzhiyun # define R600_D1GRPH_SWAP_ENDIAN_64BIT 3 96*4882a593Smuzhiyun # define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 97*4882a593Smuzhiyun # define R600_D1GRPH_RED_SEL_R 0 98*4882a593Smuzhiyun # define R600_D1GRPH_RED_SEL_G 1 99*4882a593Smuzhiyun # define R600_D1GRPH_RED_SEL_B 2 100*4882a593Smuzhiyun # define R600_D1GRPH_RED_SEL_A 3 101*4882a593Smuzhiyun # define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 102*4882a593Smuzhiyun # define R600_D1GRPH_GREEN_SEL_G 0 103*4882a593Smuzhiyun # define R600_D1GRPH_GREEN_SEL_B 1 104*4882a593Smuzhiyun # define R600_D1GRPH_GREEN_SEL_A 2 105*4882a593Smuzhiyun # define R600_D1GRPH_GREEN_SEL_R 3 106*4882a593Smuzhiyun # define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 107*4882a593Smuzhiyun # define R600_D1GRPH_BLUE_SEL_B 0 108*4882a593Smuzhiyun # define R600_D1GRPH_BLUE_SEL_A 1 109*4882a593Smuzhiyun # define R600_D1GRPH_BLUE_SEL_R 2 110*4882a593Smuzhiyun # define R600_D1GRPH_BLUE_SEL_G 3 111*4882a593Smuzhiyun # define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 112*4882a593Smuzhiyun # define R600_D1GRPH_ALPHA_SEL_A 0 113*4882a593Smuzhiyun # define R600_D1GRPH_ALPHA_SEL_R 1 114*4882a593Smuzhiyun # define R600_D1GRPH_ALPHA_SEL_G 2 115*4882a593Smuzhiyun # define R600_D1GRPH_ALPHA_SEL_B 3 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define R600_HDP_NONSURFACE_BASE 0x2c04 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define R600_BUS_CNTL 0x5420 120*4882a593Smuzhiyun # define R600_BIOS_ROM_DIS (1 << 1) 121*4882a593Smuzhiyun #define R600_CONFIG_CNTL 0x5424 122*4882a593Smuzhiyun #define R600_CONFIG_MEMSIZE 0x5428 123*4882a593Smuzhiyun #define R600_CONFIG_F0_BASE 0x542C 124*4882a593Smuzhiyun #define R600_CONFIG_APER_SIZE 0x5430 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define R600_BIF_FB_EN 0x5490 127*4882a593Smuzhiyun #define R600_FB_READ_EN (1 << 0) 128*4882a593Smuzhiyun #define R600_FB_WRITE_EN (1 << 1) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define R600_CITF_CNTL 0x200c 131*4882a593Smuzhiyun #define R600_BLACKOUT_MASK 0x00000003 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define R700_MC_CITF_CNTL 0x25c0 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define R600_ROM_CNTL 0x1600 136*4882a593Smuzhiyun # define R600_SCK_OVERWRITE (1 << 1) 137*4882a593Smuzhiyun # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 138*4882a593Smuzhiyun # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define R600_CG_SPLL_FUNC_CNTL 0x600 141*4882a593Smuzhiyun # define R600_SPLL_BYPASS_EN (1 << 3) 142*4882a593Smuzhiyun #define R600_CG_SPLL_STATUS 0x60c 143*4882a593Smuzhiyun # define R600_SPLL_CHG_STATUS (1 << 1) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define R600_BIOS_0_SCRATCH 0x1724 146*4882a593Smuzhiyun #define R600_BIOS_1_SCRATCH 0x1728 147*4882a593Smuzhiyun #define R600_BIOS_2_SCRATCH 0x172c 148*4882a593Smuzhiyun #define R600_BIOS_3_SCRATCH 0x1730 149*4882a593Smuzhiyun #define R600_BIOS_4_SCRATCH 0x1734 150*4882a593Smuzhiyun #define R600_BIOS_5_SCRATCH 0x1738 151*4882a593Smuzhiyun #define R600_BIOS_6_SCRATCH 0x173c 152*4882a593Smuzhiyun #define R600_BIOS_7_SCRATCH 0x1740 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Audio, these regs were reverse enginered, 155*4882a593Smuzhiyun * so the chance is high that the naming is wrong 156*4882a593Smuzhiyun * R6xx+ ??? */ 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Audio clocks */ 159*4882a593Smuzhiyun #define R600_AUDIO_PLL1_MUL 0x0514 160*4882a593Smuzhiyun #define R600_AUDIO_PLL1_DIV 0x0518 161*4882a593Smuzhiyun #define R600_AUDIO_PLL2_MUL 0x0524 162*4882a593Smuzhiyun #define R600_AUDIO_PLL2_DIV 0x0528 163*4882a593Smuzhiyun #define R600_AUDIO_CLK_SRCSEL 0x0534 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* Audio general */ 166*4882a593Smuzhiyun #define R600_AUDIO_ENABLE 0x7300 167*4882a593Smuzhiyun #define R600_AUDIO_TIMING 0x7344 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Audio params */ 170*4882a593Smuzhiyun #define R600_AUDIO_VENDOR_ID 0x7380 171*4882a593Smuzhiyun #define R600_AUDIO_REVISION_ID 0x7384 172*4882a593Smuzhiyun #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 173*4882a593Smuzhiyun #define R600_AUDIO_NID1_NODE_COUNT 0x738c 174*4882a593Smuzhiyun #define R600_AUDIO_NID1_TYPE 0x7390 175*4882a593Smuzhiyun #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 176*4882a593Smuzhiyun #define R600_AUDIO_SUPPORTED_CODEC 0x7398 177*4882a593Smuzhiyun #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c 178*4882a593Smuzhiyun #define R600_AUDIO_NID2_CAPS 0x73a0 179*4882a593Smuzhiyun #define R600_AUDIO_NID3_CAPS 0x73a4 180*4882a593Smuzhiyun #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* Audio conn list */ 183*4882a593Smuzhiyun #define R600_AUDIO_CONN_LIST_LEN 0x73ac 184*4882a593Smuzhiyun #define R600_AUDIO_CONN_LIST 0x73b0 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* Audio verbs */ 187*4882a593Smuzhiyun #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 188*4882a593Smuzhiyun #define R600_AUDIO_PLAYING 0x73c4 189*4882a593Smuzhiyun #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 190*4882a593Smuzhiyun #define R600_AUDIO_CONFIG_DEFAULT 0x73cc 191*4882a593Smuzhiyun #define R600_AUDIO_PIN_SENSE 0x73d0 192*4882a593Smuzhiyun #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 193*4882a593Smuzhiyun #define R600_AUDIO_STATUS_BITS 0x73d8 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400) 196*4882a593Smuzhiyun #define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400) 197*4882a593Smuzhiyun /* DCE3.2 second instance starts at 0x7800 */ 198*4882a593Smuzhiyun #define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400) 199*4882a593Smuzhiyun #define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400) 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #endif 202