Lines Matching +full:0 +full:x000fffff
34 #define HAL_SHADOW_BASE_ADDR 0x000008fc
42 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
43 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
44 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000
45 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000
46 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000
47 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000
48 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
51 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014
52 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c
96 #define HAL_TCL1_RING_HP 0x00002000
97 #define HAL_TCL1_RING_TP 0x00002004
98 #define HAL_TCL2_RING_HP 0x00002008
99 #define HAL_TCL_RING_HP 0x00002018
107 #define HAL_TCL_STATUS_RING_HP 0x00002030
110 #define HAL_REO1_GEN_ENABLE 0x00000000
111 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004
112 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
113 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
114 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
174 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194
177 #define HAL_REO_CMD_HP 0x00003020
180 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec
183 #define HAL_SW2REO_RING_HP 0x00003028
186 #define HAL_CE_DST_RING_BASE_LSB 0x00000000
187 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058
188 #define HAL_CE_DST_RING_CTRL 0x000000b0
191 #define HAL_CE_DST_RING_HP 0x00000400
192 #define HAL_CE_DST_STATUS_RING_HP 0x00000408
200 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860
201 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870
202 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048
203 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c
204 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058
205 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c
206 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
207 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
208 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
209 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
210 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084
213 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0
216 #define HAL_WBM_RELEASE_RING_BASE_LSB 0x000001d8
219 #define HAL_WBM_RELEASE_RING_HP 0x00003018
222 #define HAL_WBM0_RELEASE_RING_BASE_LSB 0x00000910
223 #define HAL_WBM1_RELEASE_RING_BASE_LSB 0x00000968
226 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0
227 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8
231 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
232 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
239 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
240 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
242 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
244 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
245 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
256 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
258 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
264 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
266 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
272 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
274 #define HAL_ADDR_LSB_REG_MASK 0xffffffff
282 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
288 #define BASE_ADDR_MATCH_TAG_VAL 0x5
290 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff
291 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff
292 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff
293 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff
294 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
295 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff
296 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff
297 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
298 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff
299 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff
300 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
301 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff
302 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff
303 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
304 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
313 HAL_SRNG_RING_ID_REO2SW1 = 0,
394 #define HAL_SRNG_REG_GRP_R0 0
446 HAL_REO_CMD_GET_QUEUE_STATS = 0,
465 HAL_REO_CMD_SUCCESS = 0,
469 HAL_REO_CMD_DRAIN = 0xff,
498 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
499 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
500 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
501 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
502 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
503 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
666 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000
668 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
757 #define HAL_HASH_ROUTING_RING_TCL 0
778 u32 rx_bitmap[8]; /* Bitmap from 0-255 */