1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2008-2011 Atheros Communications Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission to use, copy, modify, and/or distribute this software for any 5*4882a593Smuzhiyun * purpose with or without fee is hereby granted, provided that the above 6*4882a593Smuzhiyun * copyright notice and this permission notice appear in all copies. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*4882a593Smuzhiyun * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*4882a593Smuzhiyun * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*4882a593Smuzhiyun * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*4882a593Smuzhiyun * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*4882a593Smuzhiyun * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #ifndef AR9002_PHY_H 17*4882a593Smuzhiyun #define AR9002_PHY_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define AR_PHY_TEST 0x9800 20*4882a593Smuzhiyun #define PHY_AGC_CLR 0x10000000 21*4882a593Smuzhiyun #define RFSILENT_BB 0x00002000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define AR_PHY_TURBO 0x9804 24*4882a593Smuzhiyun #define AR_PHY_FC_TURBO_MODE 0x00000001 25*4882a593Smuzhiyun #define AR_PHY_FC_TURBO_SHORT 0x00000002 26*4882a593Smuzhiyun #define AR_PHY_FC_DYN2040_EN 0x00000004 27*4882a593Smuzhiyun #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 28*4882a593Smuzhiyun #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 29*4882a593Smuzhiyun /* For 25 MHz channel spacing -- not used but supported by hw */ 30*4882a593Smuzhiyun #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 31*4882a593Smuzhiyun #define AR_PHY_FC_HT_EN 0x00000040 32*4882a593Smuzhiyun #define AR_PHY_FC_SHORT_GI_40 0x00000080 33*4882a593Smuzhiyun #define AR_PHY_FC_WALSH 0x00000100 34*4882a593Smuzhiyun #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 35*4882a593Smuzhiyun #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AR_PHY_TEST2 0x9808 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AR_PHY_TIMING2 0x9810 40*4882a593Smuzhiyun #define AR_PHY_TIMING3 0x9814 41*4882a593Smuzhiyun #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 42*4882a593Smuzhiyun #define AR_PHY_TIMING3_DSC_MAN_S 17 43*4882a593Smuzhiyun #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 44*4882a593Smuzhiyun #define AR_PHY_TIMING3_DSC_EXP_S 13 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define AR_PHY_CHIP_ID_REV_0 0x80 47*4882a593Smuzhiyun #define AR_PHY_CHIP_ID_REV_1 0x81 48*4882a593Smuzhiyun #define AR_PHY_CHIP_ID_9160_REV_0 0xb0 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define AR_PHY_ACTIVE 0x981C 51*4882a593Smuzhiyun #define AR_PHY_ACTIVE_EN 0x00000001 52*4882a593Smuzhiyun #define AR_PHY_ACTIVE_DIS 0x00000000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define AR_PHY_RF_CTL2 0x9824 55*4882a593Smuzhiyun #define AR_PHY_TX_END_DATA_START 0x000000FF 56*4882a593Smuzhiyun #define AR_PHY_TX_END_DATA_START_S 0 57*4882a593Smuzhiyun #define AR_PHY_TX_END_PA_ON 0x0000FF00 58*4882a593Smuzhiyun #define AR_PHY_TX_END_PA_ON_S 8 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define AR_PHY_RF_CTL3 0x9828 61*4882a593Smuzhiyun #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 62*4882a593Smuzhiyun #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 63*4882a593Smuzhiyun #define AR_PHY_TX_END_TO_ADC_ON 0xFF000000 64*4882a593Smuzhiyun #define AR_PHY_TX_END_TO_ADC_ON_S 24 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define AR_PHY_ADC_CTL 0x982C 67*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 68*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 69*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 70*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 71*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 72*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 73*4882a593Smuzhiyun #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define AR_PHY_ADC_SERIAL_CTL 0x9830 76*4882a593Smuzhiyun #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 77*4882a593Smuzhiyun #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define AR_PHY_RF_CTL4 0x9834 80*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 81*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 82*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 83*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 84*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 85*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 86*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 87*4882a593Smuzhiyun #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define AR_PHY_TSTDAC_CONST 0x983c 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define AR_PHY_SETTLING 0x9844 92*4882a593Smuzhiyun #define AR_PHY_SETTLING_SWITCH 0x00003F80 93*4882a593Smuzhiyun #define AR_PHY_SETTLING_SWITCH_S 7 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define AR_PHY_RXGAIN 0x9848 96*4882a593Smuzhiyun #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 97*4882a593Smuzhiyun #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 98*4882a593Smuzhiyun #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 99*4882a593Smuzhiyun #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 100*4882a593Smuzhiyun #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 101*4882a593Smuzhiyun #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 102*4882a593Smuzhiyun #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 103*4882a593Smuzhiyun #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ 0x9850 106*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 107*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_ADC_S 0 108*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 109*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_PGA_S 8 110*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 111*4882a593Smuzhiyun #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define AR_PHY_FIND_SIG 0x9858 114*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 115*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRSTEP_S 12 116*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 117*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRPWR_S 18 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_LOW 0x9840 120*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRSTEP_LOW 0x00000FC0L 121*4882a593Smuzhiyun #define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define AR_PHY_AGC_CTL1 0x985C 124*4882a593Smuzhiyun #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 125*4882a593Smuzhiyun #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 126*4882a593Smuzhiyun #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 127*4882a593Smuzhiyun #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define AR_PHY_CCA 0x9864 130*4882a593Smuzhiyun #define AR_PHY_MINCCA_PWR 0x0FF80000 131*4882a593Smuzhiyun #define AR_PHY_MINCCA_PWR_S 19 132*4882a593Smuzhiyun #define AR_PHY_CCA_THRESH62 0x0007F000 133*4882a593Smuzhiyun #define AR_PHY_CCA_THRESH62_S 12 134*4882a593Smuzhiyun #define AR9280_PHY_MINCCA_PWR 0x1FF00000 135*4882a593Smuzhiyun #define AR9280_PHY_MINCCA_PWR_S 20 136*4882a593Smuzhiyun #define AR9280_PHY_CCA_THRESH62 0x000FF000 137*4882a593Smuzhiyun #define AR9280_PHY_CCA_THRESH62_S 12 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW 0x986C 140*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 141*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 142*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 143*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 144*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 145*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 146*4882a593Smuzhiyun #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define AR_PHY_SFCORR 0x9868 149*4882a593Smuzhiyun #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 150*4882a593Smuzhiyun #define AR_PHY_SFCORR_M2COUNT_THR_S 0 151*4882a593Smuzhiyun #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 152*4882a593Smuzhiyun #define AR_PHY_SFCORR_M1_THRESH_S 17 153*4882a593Smuzhiyun #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 154*4882a593Smuzhiyun #define AR_PHY_SFCORR_M2_THRESH_S 24 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 157*4882a593Smuzhiyun #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 158*4882a593Smuzhiyun #define AR_PHY_SYNTH_CONTROL 0x9874 159*4882a593Smuzhiyun #define AR_PHY_SLEEP_SCAL 0x9878 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define AR_PHY_PLL_CTL 0x987c 162*4882a593Smuzhiyun #define AR_PHY_PLL_CTL_40 0xaa 163*4882a593Smuzhiyun #define AR_PHY_PLL_CTL_40_5413 0x04 164*4882a593Smuzhiyun #define AR_PHY_PLL_CTL_44 0xab 165*4882a593Smuzhiyun #define AR_PHY_PLL_CTL_44_2133 0xeb 166*4882a593Smuzhiyun #define AR_PHY_PLL_CTL_40_2133 0xea 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */ 169*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 170*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */ 171*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */ 172*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/ 173*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/ 174*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/ 175*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 176*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/ 177*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 178*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/ 179*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 180*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI 0x0FFF0000 /* Number of reports, reg 68, bits 16-27*/ 181*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI_S 16 182*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/ 183*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI 0x10000000 /* Short repeat, reg 68, bit 28*/ 184*4882a593Smuzhiyun #define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT 0x40000000 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define AR_PHY_RX_DELAY 0x9914 187*4882a593Smuzhiyun #define AR_PHY_SEARCH_START_DELAY 0x9918 188*4882a593Smuzhiyun #define AR_PHY_RX_DELAY_DELAY 0x00003FFF 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) 191*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F 192*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 193*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 194*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 195*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 196*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 197*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 198*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 201*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 202*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 203*4882a593Smuzhiyun #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define AR_PHY_TIMING5 0x9924 206*4882a593Smuzhiyun #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 207*4882a593Smuzhiyun #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE1 0x9934 210*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE2 0x9938 211*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE_MAX 0x993c 212*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define AR_PHY_FRAME_CTL 0x9944 215*4882a593Smuzhiyun #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 216*4882a593Smuzhiyun #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define AR_PHY_TXPWRADJ 0x994C 219*4882a593Smuzhiyun #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 220*4882a593Smuzhiyun #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 221*4882a593Smuzhiyun #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 222*4882a593Smuzhiyun #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define AR_PHY_RADAR_EXT 0x9940 225*4882a593Smuzhiyun #define AR_PHY_RADAR_EXT_ENA 0x00004000 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define AR_PHY_RADAR_0 0x9954 228*4882a593Smuzhiyun #define AR_PHY_RADAR_0_ENA 0x00000001 229*4882a593Smuzhiyun #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 230*4882a593Smuzhiyun #define AR_PHY_RADAR_0_INBAND 0x0000003e 231*4882a593Smuzhiyun #define AR_PHY_RADAR_0_INBAND_S 1 232*4882a593Smuzhiyun #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 233*4882a593Smuzhiyun #define AR_PHY_RADAR_0_PRSSI_S 6 234*4882a593Smuzhiyun #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 235*4882a593Smuzhiyun #define AR_PHY_RADAR_0_HEIGHT_S 12 236*4882a593Smuzhiyun #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 237*4882a593Smuzhiyun #define AR_PHY_RADAR_0_RRSSI_S 18 238*4882a593Smuzhiyun #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 239*4882a593Smuzhiyun #define AR_PHY_RADAR_0_FIRPWR_S 24 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define AR_PHY_RADAR_1 0x9958 242*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 243*4882a593Smuzhiyun #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 244*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 245*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 246*4882a593Smuzhiyun #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 247*4882a593Smuzhiyun #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 248*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 249*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 250*4882a593Smuzhiyun #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 251*4882a593Smuzhiyun #define AR_PHY_RADAR_1_MAXLEN 0x000000FF 252*4882a593Smuzhiyun #define AR_PHY_RADAR_1_MAXLEN_S 0 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define AR_PHY_SWITCH_CHAIN_0 0x9960 255*4882a593Smuzhiyun #define AR_PHY_SWITCH_COM 0x9964 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA 0x996C 258*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 259*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 260*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 261*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_FILT2_S 3 262*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 263*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_FILT1_S 8 264*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 265*4882a593Smuzhiyun #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun #define AR_PHY_RESTART 0x9970 268*4882a593Smuzhiyun #define AR_PHY_RESTART_DIV_GC 0x001C0000 269*4882a593Smuzhiyun #define AR_PHY_RESTART_DIV_GC_S 18 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define AR_PHY_RFBUS_REQ 0x997C 272*4882a593Smuzhiyun #define AR_PHY_RFBUS_REQ_EN 0x00000001 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define AR_PHY_TIMING7 0x9980 275*4882a593Smuzhiyun #define AR_PHY_TIMING8 0x9984 276*4882a593Smuzhiyun #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 277*4882a593Smuzhiyun #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_1 0x9988 280*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_2 0x998c 281*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_3 0x9990 282*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_4 0x9994 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #define AR_PHY_BIN_MASK_1 0x9900 285*4882a593Smuzhiyun #define AR_PHY_BIN_MASK_2 0x9904 286*4882a593Smuzhiyun #define AR_PHY_BIN_MASK_3 0x9908 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define AR_PHY_MASK_CTL 0x990c 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 291*4882a593Smuzhiyun #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun #define AR_PHY_TIMING9 0x9998 294*4882a593Smuzhiyun #define AR_PHY_TIMING10 0x999c 295*4882a593Smuzhiyun #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 296*4882a593Smuzhiyun #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun #define AR_PHY_TIMING11 0x99a0 299*4882a593Smuzhiyun #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 300*4882a593Smuzhiyun #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 301*4882a593Smuzhiyun #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 302*4882a593Smuzhiyun #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define AR_PHY_RX_CHAINMASK 0x99a4 305*4882a593Smuzhiyun #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 306*4882a593Smuzhiyun #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 307*4882a593Smuzhiyun #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 310*4882a593Smuzhiyun #define AR_PHY_9285_FAST_DIV_BIAS 0x00007E00 311*4882a593Smuzhiyun #define AR_PHY_9285_FAST_DIV_BIAS_S 9 312*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 313*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_CTL 0x01000000 314*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_CTL_S 24 315*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 316*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 317*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 318*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 319*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 320*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 321*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 322*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 323*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_GAINTB_0 0 324*4882a593Smuzhiyun #define AR_PHY_9285_ANT_DIV_GAINTB_1 1 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #define ATH_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 327*4882a593Smuzhiyun #define ATH_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 328*4882a593Smuzhiyun #define ATH_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 329*4882a593Smuzhiyun #define ATH_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 330*4882a593Smuzhiyun #define ATH_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #define AR_PHY_EXT_CCA0 0x99b8 333*4882a593Smuzhiyun #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 334*4882a593Smuzhiyun #define AR_PHY_EXT_CCA0_THRESH62_S 0 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define AR_PHY_EXT_CCA 0x99bc 337*4882a593Smuzhiyun #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 338*4882a593Smuzhiyun #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 339*4882a593Smuzhiyun #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 340*4882a593Smuzhiyun #define AR_PHY_EXT_CCA_THRESH62_S 16 341*4882a593Smuzhiyun #define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00L 342*4882a593Smuzhiyun #define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define AR_PHY_EXT_MINCCA_PWR 0xFF800000 345*4882a593Smuzhiyun #define AR_PHY_EXT_MINCCA_PWR_S 23 346*4882a593Smuzhiyun #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 347*4882a593Smuzhiyun #define AR9280_PHY_EXT_MINCCA_PWR_S 16 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT 0x99c0 350*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 351*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 352*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 353*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 354*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 355*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 356*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 357*4882a593Smuzhiyun #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 358*4882a593Smuzhiyun #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun #define AR_PHY_HALFGI 0x99D0 361*4882a593Smuzhiyun #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 362*4882a593Smuzhiyun #define AR_PHY_HALFGI_DSC_MAN_S 4 363*4882a593Smuzhiyun #define AR_PHY_HALFGI_DSC_EXP 0x0000000F 364*4882a593Smuzhiyun #define AR_PHY_HALFGI_DSC_EXP_S 0 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun #define AR_PHY_CHAN_INFO_MEMORY 0x99DC 367*4882a593Smuzhiyun #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC 372*4882a593Smuzhiyun #define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define AR_PHY_M_SLEEP 0x99f0 375*4882a593Smuzhiyun #define AR_PHY_REFCLKDLY 0x99f4 376*4882a593Smuzhiyun #define AR_PHY_REFCLKPD 0x99f8 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define AR_PHY_CALMODE 0x99f0 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define AR_PHY_CALMODE_IQ 0x00000000 381*4882a593Smuzhiyun #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 382*4882a593Smuzhiyun #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 383*4882a593Smuzhiyun #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 386*4882a593Smuzhiyun #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 387*4882a593Smuzhiyun #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 388*4882a593Smuzhiyun #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun #define AR_PHY_CURRENT_RSSI 0x9c1c 391*4882a593Smuzhiyun #define AR9280_PHY_CURRENT_RSSI 0x9c3c 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #define AR_PHY_RFBUS_GRANT 0x9C20 394*4882a593Smuzhiyun #define AR_PHY_RFBUS_GRANT_EN 0x00000001 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 397*4882a593Smuzhiyun #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun #define AR_PHY_CHAN_INFO_GAIN 0x9CFC 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun #define AR_PHY_MODE 0xA200 402*4882a593Smuzhiyun #define AR_PHY_MODE_ASYNCFIFO 0x80 403*4882a593Smuzhiyun #define AR_PHY_MODE_AR2133 0x08 404*4882a593Smuzhiyun #define AR_PHY_MODE_AR5111 0x00 405*4882a593Smuzhiyun #define AR_PHY_MODE_AR5112 0x08 406*4882a593Smuzhiyun #define AR_PHY_MODE_DYNAMIC 0x04 407*4882a593Smuzhiyun #define AR_PHY_MODE_RF2GHZ 0x02 408*4882a593Smuzhiyun #define AR_PHY_MODE_RF5GHZ 0x00 409*4882a593Smuzhiyun #define AR_PHY_MODE_CCK 0x01 410*4882a593Smuzhiyun #define AR_PHY_MODE_OFDM 0x00 411*4882a593Smuzhiyun #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define AR_PHY_CCK_TX_CTRL 0xA204 414*4882a593Smuzhiyun #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 415*4882a593Smuzhiyun #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 416*4882a593Smuzhiyun #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT 0xA208 419*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 420*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 421*4882a593Smuzhiyun /* [12:6] settling time for antenna switch */ 422*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 423*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 424*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 425*4882a593Smuzhiyun #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ 0xA20C 428*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 429*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 430*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 431*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 432*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 433*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 436*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 437*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 438*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 439*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 440*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 441*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 442*4882a593Smuzhiyun #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun #define AR_PHY_CCK_RXCTRL4 0xA21C 445*4882a593Smuzhiyun #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 446*4882a593Smuzhiyun #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #define AR_PHY_DAG_CTRLCCK 0xA228 449*4882a593Smuzhiyun #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 450*4882a593Smuzhiyun #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 451*4882a593Smuzhiyun #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun #define AR_PHY_FORCE_CLKEN_CCK 0xA22C 454*4882a593Smuzhiyun #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE3 0xA234 457*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE4 0xA238 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #define AR_PHY_SCRM_SEQ_XR 0xA23C 460*4882a593Smuzhiyun #define AR_PHY_HEADER_DETECT_XR 0xA240 461*4882a593Smuzhiyun #define AR_PHY_CHIRP_DETECTED_XR 0xA244 462*4882a593Smuzhiyun #define AR_PHY_BLUETOOTH 0xA254 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun #define AR_PHY_TPCRG1 0xA258 465*4882a593Smuzhiyun #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 466*4882a593Smuzhiyun #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 469*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 470*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 471*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 472*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 473*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 476*4882a593Smuzhiyun #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL4 0xa264 479*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 480*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 481*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE 482*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL6_0 0xa270 485*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL6_1 0xb270 486*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 487*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL7 0xa274 490*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 491*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL8 0xa278 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL9 0xa27C 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL10 0xa394 498*4882a593Smuzhiyun #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 499*4882a593Smuzhiyun #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 500*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 501*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun #define AR_PHY_TX_GAIN_TBL1 0xa300 504*4882a593Smuzhiyun #define AR_PHY_TX_GAIN 0x0007F000 505*4882a593Smuzhiyun #define AR_PHY_TX_GAIN_S 12 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 508*4882a593Smuzhiyun #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 509*4882a593Smuzhiyun #define AR_PHY_CH0_TX_PWRCTRL12 0xa3dc 510*4882a593Smuzhiyun #define AR_PHY_CH0_TX_PWRCTRL13 0xa3e0 511*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 512*4882a593Smuzhiyun #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 515*4882a593Smuzhiyun #define AR_PHY_MASK2_M_31_45 0xa3a4 516*4882a593Smuzhiyun #define AR_PHY_MASK2_M_16_30 0xa3a8 517*4882a593Smuzhiyun #define AR_PHY_MASK2_M_00_15 0xa3ac 518*4882a593Smuzhiyun #define AR_PHY_MASK2_P_15_01 0xa3b8 519*4882a593Smuzhiyun #define AR_PHY_MASK2_P_30_16 0xa3bc 520*4882a593Smuzhiyun #define AR_PHY_MASK2_P_45_31 0xa3c0 521*4882a593Smuzhiyun #define AR_PHY_MASK2_P_61_45 0xa3c4 522*4882a593Smuzhiyun #define AR_PHY_SPUR_REG 0x994c 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 525*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 528*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) 529*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 530*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 531*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 532*4882a593Smuzhiyun #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun #define AR_PHY_PILOT_MASK_01_30 0xa3b0 535*4882a593Smuzhiyun #define AR_PHY_PILOT_MASK_31_60 0xa3b4 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun #define AR_PHY_CHANNEL_MASK_01_30 0x99d4 538*4882a593Smuzhiyun #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun #define AR_PHY_ANALOG_SWAP 0xa268 541*4882a593Smuzhiyun #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun #define AR_PHY_TPCRG5 0xA26C 544*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 545*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 546*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 547*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 548*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 549*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 550*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 551*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 552*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 553*4882a593Smuzhiyun #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun /* Carrier leak calibration control, do it after AGC calibration */ 556*4882a593Smuzhiyun #define AR_PHY_CL_CAL_CTL 0xA358 557*4882a593Smuzhiyun #define AR_PHY_CL_CAL_ENABLE 0x00000002 558*4882a593Smuzhiyun #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE5 0xA38C 561*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE6 0xA390 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun #define AR_PHY_CAL_CHAINMASK 0xA39C 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun #define AR_PHY_POWER_TX_SUB 0xA3C8 566*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE7 0xA3CC 567*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE8 0xA3D0 568*4882a593Smuzhiyun #define AR_PHY_POWER_TX_RATE9 0xA3D4 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #define AR_PHY_XPA_CFG 0xA3D8 571*4882a593Smuzhiyun #define AR_PHY_FORCE_XPA_CFG 0x000000001 572*4882a593Smuzhiyun #define AR_PHY_FORCE_XPA_CFG_S 0 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun #define AR_PHY_CH1_CCA 0xa864 575*4882a593Smuzhiyun #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 576*4882a593Smuzhiyun #define AR_PHY_CH1_MINCCA_PWR_S 19 577*4882a593Smuzhiyun #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 578*4882a593Smuzhiyun #define AR9280_PHY_CH1_MINCCA_PWR_S 20 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun #define AR_PHY_CH2_CCA 0xb864 581*4882a593Smuzhiyun #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 582*4882a593Smuzhiyun #define AR_PHY_CH2_MINCCA_PWR_S 19 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun #define AR_PHY_CH1_EXT_CCA 0xa9bc 585*4882a593Smuzhiyun #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 586*4882a593Smuzhiyun #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 587*4882a593Smuzhiyun #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 588*4882a593Smuzhiyun #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun #define AR_PHY_CH2_EXT_CCA 0xb9bc 591*4882a593Smuzhiyun #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 592*4882a593Smuzhiyun #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90 595*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100 596*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100 597*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110 598*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80 599*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_9280_2GHZ -112 602*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_9280_5GHZ -112 603*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ -127 604*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ -122 605*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ -97 606*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ -102 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_9285_2GHZ -118 609*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ -127 610*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ -108 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_9271_2GHZ -118 613*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ -127 614*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ -116 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun #define AR_PHY_CCA_NOM_VAL_9287_2GHZ -112 617*4882a593Smuzhiyun #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ -127 618*4882a593Smuzhiyun #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ -97 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun #endif 621