| /rk3399_ARM-atf/lib/compiler-rt/builtins/ |
| H A D | ctzdi2.c | 30 dwords x; in __ctzdi2() local
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| /rk3399_ARM-atf/include/lib/libc/ |
| H A D | stdlib.h | 21 #define isspace(x) (((x) == ' ') || ((x) == '\r') || ((x) == '\n') || \ argument
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| /rk3399_ARM-atf/drivers/imx/usdhc/ |
| H A D | imx_usdhc.h | 26 #define BLKATT_BLKCNT(x) (((x) << 16U) & GENMASK_32(31U, 16U)) argument
27 #define BLKATT_BLKSIZE(x) ((x) & GENMASK_32(12U, 0U)) argument
35 #define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U) argument
36 #define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U) argument
64 #define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U) argument
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| /rk3399_ARM-atf/include/dt-bindings/interrupt-controller/ |
| H A D | arm-gic.h | 24 #define GIC_CPU_MASK_RAW(x) ((x) << 8) argument
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch_helpers.h | 261 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ argument
263 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ argument
265 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ argument
268 #define set_cntp_ctl_enable(x) ((x) |= U(1) << CNTP_CTL_ENABLE_SHIFT) argument
269 #define set_cntp_ctl_imask(x) ((x) |= U(1) << CNTP_CTL_IMASK_SHIFT) argument
271 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) argument
272 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) argument
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| /rk3399_ARM-atf/plat/imx/common/include/ |
| H A D | imx8_lpuart.h | 43 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SH… argument
47 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SH… argument
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| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_emac.h | 20 #define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8)) argument
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| /rk3399_ARM-atf/include/lib/gpt_rme/ |
| H A D | gpt_rme.h | 153 #define SET_GPCCR_PGS(x) (((x) & GPCCR_PGS_MASK) << GPCCR_PGS_SHIFT) argument
164 #define SET_GPCCR_SH(x) (((x) & GPCCR_SH_MASK) << GPCCR_SH_SHIFT) argument
175 #define SET_GPCCR_ORGN(x) (((x) & GPCCR_ORGN_MASK) << GPCCR_ORGN_SHIFT) argument
187 #define SET_GPCCR_IRGN(x) (((x) & GPCCR_IRGN_MASK) << GPCCR_IRGN_SHIFT) argument
199 #define SET_GPCCR_PPS(x) (((x) & GPCCR_PPS_MASK) << GPCCR_PPS_SHIFT) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/crypt/ |
| H A D | crypt.c | 24 #define GET_L32(x) ((uint32_t)(x & 0xffffffff)) argument
25 #define GET_H32(x) ((uint32_t)((x >> 32) & 0xffffffff)) argument
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| /rk3399_ARM-atf/plat/intel/soc/common/soc/ |
| H A D | socfpga_handoff.c | 13 #define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \ argument
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| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | stm32mp_rifsc_regs.h | 19 #define _RIFSC_RIMC_ATTR(x) (U(0xC10) + U(0x4) * (x)) argument
20 #define _RIFSC_PPSR(x) (U(0xFB0) + U(0x4) * (x)) argument
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| /rk3399_ARM-atf/fdts/ |
| H A D | stmm_common.dtsi | 30 #define PAGE_ALIGN(x) ((x) & ~(PAGE_SHIFT -1)) argument
31 #define PAGE_ALIGN_UP(x) ((x + (PAGE_SHIFT - 1)) & ~(PAGE_SHIFT - 1)) argument
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| /rk3399_ARM-atf/lib/libfdt/ |
| H A D | libfdt_internal.h | 10 #define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) argument
11 #define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) argument
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| /rk3399_ARM-atf/drivers/marvell/mc_trustzone/ |
| H A D | mc_trustzone.h | 16 #define TZ_PERM(x) ((x) << 1) argument
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/version/notifier/v1/ |
| H A D | mt_spm_sspm_notifier.c | 13 #define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/notifier/ |
| H A D | mt_spm_sspm_notifier.c | 14 #define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/notifier/ |
| H A D | mt_spm_sspm_notifier.c | 14 #define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x) argument
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| /rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/ |
| H A D | pmic_wrap_init_common.h | 21 #define GET_SWINF_INIT_DONE(x) ((x>>15) & 0x00000001) argument
22 #define GET_WACS_FSM(x) ((x >> 1) & 0x7) argument
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| /rk3399_ARM-atf/lib/extensions/sve/ |
| H A D | sve.c | 23 #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) argument
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| /rk3399_ARM-atf/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 127 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
128 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
129 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
130 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
131 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
132 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
133 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
134 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
463 #define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) argument
464 #define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) argument
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| /rk3399_ARM-atf/include/lib/ |
| H A D | utils_def.h | 17 #define IS_POWER_OF_TWO(x) \ argument
109 #define MIN(x, y) __extension__ ({ \ argument
116 #define MAX(x, y) __extension__ ({ \ argument
123 #define CLAMP(x, min, max) __extension__ ({ \ argument
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| /rk3399_ARM-atf/plat/intel/soc/common/drivers/ccu/ |
| H A D | ncore_ccu.h | 430 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ argument
432 #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ argument
436 #define CSUIDR_NUM_CMI(x) (((x) & 0x3F000000) >> 24) argument
437 #define CSUIDR_NUM_DIR(x) (((x) & 0x003F0000) >> 16) argument
438 #define CSUIDR_NUM_NCB(x) (((x) & 0x00003F00) >> 8) argument
439 #define CSUIDR_NUM_CAI(x) (((x) & 0x0000007F) >> 0) argument
440 #define CSIDR_NUM_SF(x) (((x) & 0x007C0000) >> 18) argument
441 #define SNOOP_FILTER_ID(x) (((x) << 16)) argument
442 #define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) argument
443 #define CACHING_AGENT_TYPE(x) (((x) & 0xF0000) >> 16) argument
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| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | plat_common.h | 11 #define __bf_shf(x) (__builtin_ffsll(x) - 1U) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/notifier/ |
| H A D | mt_spm_sspm_notifier.c | 14 #define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x) argument
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| /rk3399_ARM-atf/drivers/renesas/common/ |
| H A D | ddr_regs.h | 44 #define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) argument
77 #define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) argument
83 #define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) argument
158 #define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x)) argument
159 #define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x)) argument
160 #define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x)) argument
161 #define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x)) argument
229 #define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) argument
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