1*d603fd30STien Hock, Loh /* 2*d603fd30STien Hock, Loh * Copyright (c) 2020, Intel Corporation. All rights reserved. 3*d603fd30STien Hock, Loh * 4*d603fd30STien Hock, Loh * SPDX-License-Identifier: BSD-3-Clause 5*d603fd30STien Hock, Loh */ 6*d603fd30STien Hock, Loh 7*d603fd30STien Hock, Loh #ifndef SOCFPGA_EMAC_H 8*d603fd30STien Hock, Loh #define SOCFPGA_EMAC_H 9*d603fd30STien Hock, Loh 10*d603fd30STien Hock, Loh /* EMAC PHY Mode */ 11*d603fd30STien Hock, Loh 12*d603fd30STien Hock, Loh #define PHY_INTERFACE_MODE_GMII_MII 0 13*d603fd30STien Hock, Loh #define PHY_INTERFACE_MODE_RGMII 1 14*d603fd30STien Hock, Loh #define PHY_INTERFACE_MODE_RMII 2 15*d603fd30STien Hock, Loh #define PHY_INTERFACE_MODE_RESET 3 16*d603fd30STien Hock, Loh 17*d603fd30STien Hock, Loh /* Mask Definitions */ 18*d603fd30STien Hock, Loh 19*d603fd30STien Hock, Loh #define PHY_INTF_SEL_MSK 0x3 20*d603fd30STien Hock, Loh #define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8)) 21*d603fd30STien Hock, Loh 22*d603fd30STien Hock, Loh void socfpga_emac_init(void); 23*d603fd30STien Hock, Loh 24*d603fd30STien Hock, Loh #endif /* SOCFPGA_EMAC_H */ 25