| adf73ae2 | 13-Dec-2024 |
Hope Wang <hope.wang@mediatek.corp-partner.google.com> |
feat(mt8196): add SPMI driver
Add SPMI and PMIF driver for PMIC communication
Change-Id: Iad1d90381d6dad6b3e92fd9d6a3ce02fa11d15f1 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.c
feat(mt8196): add SPMI driver
Add SPMI and PMIF driver for PMIC communication
Change-Id: Iad1d90381d6dad6b3e92fd9d6a3ce02fa11d15f1 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
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| d4e6f98d | 13-Dec-2024 |
Hope Wang <hope.wang@mediatek.corp-partner.google.com> |
feat(mt8196): add PMIC driver
1. Add PMIC shutdown API 2. Add PMIC low power settings
Change-Id: I634a60fa3e2a74a6031df9fe59e2f52956ef7114 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.
feat(mt8196): add PMIC driver
1. Add PMIC shutdown API 2. Add PMIC low power settings
Change-Id: I634a60fa3e2a74a6031df9fe59e2f52956ef7114 Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
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| faa8c656 | 09-Jan-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
docs: updates to LTS
Adding updates to LTS process -
- This is based on review comments in here - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34069/3/docs/lts.rst#37 - Based on
docs: updates to LTS
Adding updates to LTS process -
- This is based on review comments in here - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/34069/3/docs/lts.rst#37 - Based on discussions with other LTS maintainers.
Change-Id: Iafc606a66ea3ea69c51b433867b5025b8debebe9 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| d39c2f38 | 12-Dec-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
docs: add inital lts doc
Ref: https://linaro.atlassian.net/browse/TFC-669
The initial LTS document was created as pdf and was maintained in a shared folder location, to avoid pdf getting lost and t
docs: add inital lts doc
Ref: https://linaro.atlassian.net/browse/TFC-669
The initial LTS document was created as pdf and was maintained in a shared folder location, to avoid pdf getting lost and trying to find where it is we decided to have LTS details part of docs in TF-A.
This patch directly reflects the data from pdf attached to TFC-669. Any improvements or amends to this will be done at later phases based on LTS maintainers comments and agreements.
Change-Id: I1434c29f0236161d2a127596e2cc528bf4cc3e85 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| e14ae4b3 | 06-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(xilinx): dcc console tests failing
The commit a6485b2b3b2c ("refactor(delay-timer): add timer callback functions") is breaking DCC console due to uninitialized timer ops structure. Fix it by mov
fix(xilinx): dcc console tests failing
The commit a6485b2b3b2c ("refactor(delay-timer): add timer callback functions") is breaking DCC console due to uninitialized timer ops structure. Fix it by moving generic delay timer init prior to console setup to make sure that time is setup before DCC console setup.
Fixes: a6485b2b3b2c ("refactor(delay-timer): add timer callback functions")
Change-Id: I67910332773741c0b08f02feb232efab6356db12 Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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| 422b181f | 17-Jan-2025 |
Yann Gautier <yann.gautier@st.com> |
fix(build): do not force PLAT in plat_helpers.mk
After the change to allow overriding platform specific defaults [1], the PLAT macro is forced to DEFAULT_PLAT in plat_helpers.mk. But this makefile i
fix(build): do not force PLAT in plat_helpers.mk
After the change to allow overriding platform specific defaults [1], the PLAT macro is forced to DEFAULT_PLAT in plat_helpers.mk. But this makefile is also called for tools. For example in fiptool makefile, as PLAT is reset to default plat (fvp), we cannot use specific platforms plat_fiptool.mk files. Put back the setting of PLAT macro in Makefile.
[1]: 1b2fb6adb5 feat(build): add ability to define platform specific defaults
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Iadf8bc7fc831a728a9688d0afdd163c8dda737e5
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| 6d415de8 | 07-Mar-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(bl32): flush before console switch state
Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so that this becomes the last call before bl32/sp_min exits. This also ensures that
refactor(bl32): flush before console switch state
Move console_switch_state(CONSOLE_FLAG_RUNTIME) to sp_min_main() so that this becomes the last call before bl32/sp_min exits. This also ensures that console_flush() is called before switching console state to runtime.
This patch mimics the behavior of console_switch_state() call in BL31 per this patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26771/4.
Change-Id: I5b562d02706b19bb8b14154be97b6e9ef4e2fd3b Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| b8ac81c7 | 20-Jan-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "chore(fvp): use correct dts for dynamiq cores" into integration |
| d6dccfb0 | 20-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "build: remove Windows compatibility layer" into integration |
| 3ab2df8d | 16-Jan-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "chore(deps): bump the pip group across 2 directories with 1 update" into integration |
| a1ff78f5 | 16-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(smmu): set root port CR0 GPCEN before ACCESSEN" into integration |
| f532cd30 | 15-Jan-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration
* changes: perf(psci): pass my_core_pos around instead of calling it repeatedly refactor(psci): move timestamp co
Merge changes I137f69be,Ia2e7168f,I0e569d12,I614272ec,Ib68293f2 into integration
* changes: perf(psci): pass my_core_pos around instead of calling it repeatedly refactor(psci): move timestamp collection to psci_pwrdown_cpu refactor(psci): factor common code out of the standby finisher refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state docs(psci): drop outdated cache maintenance comment
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| efe18729 | 15-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(mops): enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1" into integration |
| 1261f0aa | 15-Jan-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(mediatek): covert MTK_BL to uppercase for the build" into integration |
| 3f6d4794 | 04-Nov-2024 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
fix(zynqmp): modify function to have single return
This corrects the MISRA violation C2012-15.5: A function should have a single point of exit at the end. Introduced a temporary variable to store th
fix(zynqmp): modify function to have single return
This corrects the MISRA violation C2012-15.5: A function should have a single point of exit at the end. Introduced a temporary variable to store the return value to ensure single return for the function.
Change-Id: Ibff3df16b4c591384467771bc7cb316f1773f1ea Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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| 66569a76 | 03-Jan-2025 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
fix(versal2): update DDR address map
Update DDR address map of BL32, BL33 and transfer list to support AMD Versal Gen 2 platform's new memory map.
Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d0
fix(versal2): update DDR address map
Update DDR address map of BL32, BL33 and transfer list to support AMD Versal Gen 2 platform's new memory map.
Change-Id: I757b2f67270034c8a3140e4bb0ac4d7e88b5d055 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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| c7105798 | 14-Jan-2025 |
Gavin Liu <gavin.liu@mediatek.corp-partner.google.com> |
fix(mediatek): covert MTK_BL to uppercase for the build
The build macro no longer coverts variable names to uppercase. We need to convert it to uppercase to pass it on.
Change-Id: If808fc77bce71d57
fix(mediatek): covert MTK_BL to uppercase for the build
The build macro no longer coverts variable names to uppercase. We need to convert it to uppercase to pass it on.
Change-Id: If808fc77bce71d575e2d43ff83c4d9bcdcc52326 Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
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| 6b8df7b9 | 09-Jan-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(mops): enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1
FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2. However, in configurations where NS_EL2 is not enabled, EL3 must set th
feat(mops): enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1
FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2. However, in configurations where NS_EL2 is not enabled, EL3 must set the HCRX_EL2.MSCEn bit to 1 to enable the feature.
This patch ensures FEAT_MOPS is enabled by setting HCRX_EL2.MSCEn to 1.
Change-Id: Ic4960e0cc14a44279156b79ded50de475b3b21c5 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
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| 624ffe51 | 14-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "nxp-s32g274a/enable-mmu" into integration
* changes: feat(s32g274a): split early clock initialization feat(s32g274a): enable MMU for BL31 stage feat(s32g274a): dynami
Merge changes from topic "nxp-s32g274a/enable-mmu" into integration
* changes: feat(s32g274a): split early clock initialization feat(s32g274a): enable MMU for BL31 stage feat(s32g274a): dynamically map GIC regions feat(s32g274a): enable MMU for BL2 stage feat(s32g274a): dynamically map siul2 and fip img feat(s32g274a): map each image before its loading feat(nxp-clk): dynamic map of the clock modules feat(s32g274a): increase the number of MMU regions feat(s32g274a): add console mapping
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| c3273703 | 13-Jan-2025 |
Chris Kay <chris.kay@arm.com> |
build: remove Windows compatibility layer
For a couple of releases now we have officially withdrawn support for building TF-A on Windows using the native environment, relying instead on POSIX emulat
build: remove Windows compatibility layer
For a couple of releases now we have officially withdrawn support for building TF-A on Windows using the native environment, relying instead on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.
This change removes the remainder of the OS compatibility layer entirely, and migrates the build system over to explicitly relying on a POSIX environment.
Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 42f024ab | 14-Jan-2025 |
dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> |
chore(deps): bump the pip group across 2 directories with 1 update
Bumps the pip group with 1 update in the / directory: [virtualenv](https://github.com/pypa/virtualenv). Bumps the pip group with 1
chore(deps): bump the pip group across 2 directories with 1 update
Bumps the pip group with 1 update in the / directory: [virtualenv](https://github.com/pypa/virtualenv). Bumps the pip group with 1 update in the /tools/tlc directory: [virtualenv](https://github.com/pypa/virtualenv).
Updates `virtualenv` from 20.26.4 to 20.26.6 - [Release notes](https://github.com/pypa/virtualenv/releases) - [Changelog](https://github.com/pypa/virtualenv/blob/main/docs/changelog.rst) - [Commits](https://github.com/pypa/virtualenv/compare/20.26.4...20.26.6)
Updates `virtualenv` from 20.26.5 to 20.26.6 - [Release notes](https://github.com/pypa/virtualenv/releases) - [Changelog](https://github.com/pypa/virtualenv/blob/main/docs/changelog.rst) - [Commits](https://github.com/pypa/virtualenv/compare/20.26.4...20.26.6)
--- updated-dependencies: - dependency-name: virtualenv dependency-type: indirect dependency-group: pip - dependency-name: virtualenv dependency-type: indirect dependency-group: pip ...
Change-Id: I368cd2a93d5e682f6117170d8cd8c7fa696a38d5 Signed-off-by: dependabot[bot] <support@github.com> Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 61b5ef21 | 27-Nov-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): split early clock initialization
Initializing all early clocks before the MMU is enabled can impact boot time. Therefore, splitting the setup into A53 clocks and peripheral clocks ca
feat(s32g274a): split early clock initialization
Initializing all early clocks before the MMU is enabled can impact boot time. Therefore, splitting the setup into A53 clocks and peripheral clocks can be beneficial, with the peripheral clocks configured after fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| e2ae6cec | 26-Nov-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): enable MMU for BL31 stage
Enable the MMU and add two entries to map the BL31 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularit
feat(s32g274a): enable MMU for BL31 stage
Enable the MMU and add two entries to map the BL31 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity during the porting process.
Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| 5680f81c | 26-Nov-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): dynamically map GIC regions
Dynamically add entries for the GIC distributor and all its redistributors for the cases when the platform is booted using enabled MMU.
Change-Id: Ia810e
feat(s32g274a): dynamically map GIC regions
Dynamically add entries for the GIC distributor and all its redistributors for the cases when the platform is booted using enabled MMU.
Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| eb4d4185 | 26-Nov-2024 |
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> |
feat(s32g274a): enable MMU for BL2 stage
Enable the MMU and add two entries to map the BL2 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity
feat(s32g274a): enable MMU for BL2 stage
Enable the MMU and add two entries to map the BL2 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity during the porting process.
Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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