feat(stm32mp1): add "Boot mode" management for STM32MP13

Add new APIs to enter and exit "boot mode".

In this mode a potential tamper won't block access or reset
the secure IPs needed while boot, wi

feat(stm32mp1): add "Boot mode" management for STM32MP13

Add new APIs to enter and exit "boot mode".

In this mode a potential tamper won't block access or reset
the secure IPs needed while boot, without this mode a dead
lock may occurs.

Change-Id: Iad60d4a0420ec125b842a285f73a20eb54cd1828
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

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feat(stm32mp1): manage HSLV on STM32MP13

On STM32MP13, the high speed mode for pads in low voltage is different
from STM32MP15. Each peripheral supporting the feature has its own
register.
Special c

feat(stm32mp1): manage HSLV on STM32MP13

On STM32MP13, the high speed mode for pads in low voltage is different
from STM32MP15. Each peripheral supporting the feature has its own
register.
Special care is taken for SDMMC peripherals. The HSLV mode is enabled
only if the max voltage for the pads is lower or equal to 1.8V.

Change-Id: Id94d2cca17dd4aca4d764230a643b2bb9a5f3342
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): add sdmmc compatible in platform define

Add DT_SDMMC2_COMPAT define in stm32mp1_def.h file in platform.
It allows the use of the compatible in platform code.

Change-Id: I535ad67dd13

feat(stm32mp1): add sdmmc compatible in platform define

Add DT_SDMMC2_COMPAT define in stm32mp1_def.h file in platform.
It allows the use of the compatible in platform code.

Change-Id: I535ad67dd133bab59cf81881adaef42d8e88632c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): update IO compensation on STM32MP13

On STM32MP13, two new SD1 and SD2 IO compensations cells are added,
for SDMMC1 and SDMMC2. They have to be managed the same way as the
main compen

feat(stm32mp1): update IO compensation on STM32MP13

On STM32MP13, two new SD1 and SD2 IO compensations cells are added,
for SDMMC1 and SDMMC2. They have to be managed the same way as the
main compensation cell.

Change-Id: Ib7aa648d65fc98e1613bfb46b0e7dd568fd21002
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): call pmic_voltages_init() in platform init

The nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V
on STM32MP13. VDDCORE should be set at 1.25V as well.
This is necessa

feat(stm32mp1): call pmic_voltages_init() in platform init

The nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V
on STM32MP13. VDDCORE should be set at 1.25V as well.
This is necessary, as the PMIC values in its NVMEM are 1.2V.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I3c24fe4cd68c7bf143cf9318ab38a15d6d41b5d2

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feat(stm32mp1): update CFG0 OTP for STM32MP13

This field is now declared on the 10 LSB bits on STM32MP13.
Several possible values are specified in the Reference Manual, and
indicate an open or close

feat(stm32mp1): update CFG0 OTP for STM32MP13

This field is now declared on the 10 LSB bits on STM32MP13.
Several possible values are specified in the Reference Manual, and
indicate an open or closed device. Other values lead to a system panic.

Change-Id: I697124a21db66a56e7e223d601aa7cf44bb183c4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp1): usb descriptor update for STM32MP13

Update USB and DFU descriptor used for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I6e8111d279f49400a72baa12f

feat(stm32mp1): usb descriptor update for STM32MP13

Update USB and DFU descriptor used for STM32MP13x

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I6e8111d279f49400a72baa12ff39f140d97e1c70

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feat(st-clock): add clock driver for STM32MP13

Add new clock driver for STM32MP13. Split the include file to manage
either STM32MP13 or STM32MP15.

Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e9

feat(st-clock): add clock driver for STM32MP13

Add new clock driver for STM32MP13. Split the include file to manage
either STM32MP13 or STM32MP15.

Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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feat(stm32mp1): get CPU info from SYSCFG on STM32MP13

The IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is
always accessible, get chip ID and revision ID from there on STM32MP13.

Chan

feat(stm32mp1): get CPU info from SYSCFG on STM32MP13

The IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is
always accessible, get chip ID and revision ID from there on STM32MP13.

Change-Id: Ib0b6e8f68a2934a45ec0012f69db6c12a60adb17
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(tegra194/ras): remove incorrect erxctlr assert

The ERXCTLR_EL1 register reads are RES0 for some error records
leading to a false assert on a read back.

This patch removes the assert on reading

fix(tegra194/ras): remove incorrect erxctlr assert

The ERXCTLR_EL1 register reads are RES0 for some error records
leading to a false assert on a read back.

This patch removes the assert on reading back the ERXCTLR_EL1
register to fix this issue.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0cab30b12656a800ba87b8bb94b4c67a2331dee6

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Merge "fix(layerscape): update WA for Errata A-050426" into integration

feat(stm32mp1): use only one filter for TZC400 on STM32MP13

On STM32MP13, there is only 1 DDR port, hence only 1 TZC400 filter.

Change-Id: I4f6750022cdaf658cd209a4bf48a6cdb0717020e
Signed-off-by: Y

feat(stm32mp1): use only one filter for TZC400 on STM32MP13

On STM32MP13, there is only 1 DDR port, hence only 1 TZC400 filter.

Change-Id: I4f6750022cdaf658cd209a4bf48a6cdb0717020e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): add a second fixed regulator

Increase the fixed regulator number that needs to be
2 for STM32MP13.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ica990fe9a64

feat(stm32mp1): add a second fixed regulator

Increase the fixed regulator number that needs to be
2 for STM32MP13.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ica990fe9a6494b76aed763d2d353f5234fed7cea

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feat(stm32mp1): adaptations for STM32MP13 image header

The header must now include by default at least an extra padding
header, increasing the size of the header to 512 bytes (0x200).
This header wi

feat(stm32mp1): adaptations for STM32MP13 image header

The header must now include by default at least an extra padding
header, increasing the size of the header to 512 bytes (0x200).
This header will be placed at the end of SRAM3 by BootROM, letting
the whole SYSRAM to TF-A.
The boot context is now placed in SRAM2, hence this memory has to be
mapped in BL2 MMU. This mapping is done for all SRAMs in a 2MB area.

Change-Id: I50fcd43ecd0ba2076292b057566efe6809b9971a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): update boot API for header v2.0

Add the new field for the new header v2.0.
Force MP13 platform to use v2.0.
Removing unused fields in boot_api_context_t for STM32MP13.

Signed-off-by

feat(stm32mp1): update boot API for header v2.0

Add the new field for the new header v2.0.
Force MP13 platform to use v2.0.
Removing unused fields in boot_api_context_t for STM32MP13.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iac81aad9a939c1f305184e335e0a907ac69071df

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feat(stm32mp1): update IP addresses for STM32MP13

Add the IP addresses that are STM32MP13 and update the ones for
which the base address has changed.

Signed-off-by: Yann Gautier <yann.gautier@st.co

feat(stm32mp1): update IP addresses for STM32MP13

Add the IP addresses that are STM32MP13 and update the ones for
which the base address has changed.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iea71a491da36f721bfd3fbfb010177e2a6a57281

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feat(stm32mp1): add part numbers for STM32MP13

Add the new part numbers and adapt the functions that use them.
There is no package number in OTP as they all share the same GPIO
banks.
This part is t

feat(stm32mp1): add part numbers for STM32MP13

Add the new part numbers and adapt the functions that use them.
There is no package number in OTP as they all share the same GPIO
banks.
This part is then stubbed for STM32MP13.

Change-Id: I13414326b140119aece662bf8d82b387dece0dcc
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13

On STM32MP13, the chip revision Z is 0x1001, contrary to STM32MP15,
for which it was 0x2001.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Cha

feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13

On STM32MP13, the chip revision Z is 0x1001, contrary to STM32MP15,
for which it was 0x2001.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If65482e824b169282abb5e26ca91e16ef7640b52

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feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13

The backup register used on STM32MP15 to save the boot interface for
the next boot stage was 20. It is now saved in backup register 30
on STM32M

feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13

The backup register used on STM32MP15 to save the boot interface for
the next boot stage was 20. It is now saved in backup register 30
on STM32MP13.

Change-Id: Ibd051ff2eca7202184fa428ed57ecd4ae7388bd8
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): stm32mp_is_single_core() for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, always return true in
stm32mp_is_single_core() function.

Change-Id: Icf36eaa887bdf314137eda07c5751cea8c95

feat(stm32mp1): stm32mp_is_single_core() for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, always return true in
stm32mp_is_single_core() function.

Change-Id: Icf36eaa887bdf314137eda07c5751cea8c950143
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): remove unsupported features on STM32MP13

* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.
* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1
and reset fr

feat(stm32mp1): remove unsupported features on STM32MP13

* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.
* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1
and reset from MCU traces
* There is no MCU on STM32MP13. Put MCU security management
under STM32MP15 flag.
* The authentication feature is not supported yet on STM32MP13,
put the code under SPM32MP15 flag.
* On STM32MP13, the monotonic counter is managed in ROM code, keep
the monotonic counter update just for STM32MP15.
* SYSCFG: put registers not present on STM32MP13 under STM32MP15
flag, as the code that manages them.
* PMIC: use ldo3 during DDR configuration only for STM32MP15
* Reset UART pins on USB boot is no more required.

Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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feat(stm32mp1): update memory mapping for STM32MP13

SYSRAM is only 128KB and starts at 0x2FFE0000.
SRAMs are added.
BL2 code and DTB sizes are also reduced to fit in 128KB.

Change-Id: I25da99ef5c08

feat(stm32mp1): update memory mapping for STM32MP13

SYSRAM is only 128KB and starts at 0x2FFE0000.
SRAMs are added.
BL2 code and DTB sizes are also reduced to fit in 128KB.

Change-Id: I25da99ef5c08f8008ff00d38248d61b6045adad4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): introduce new flag for STM32MP13

STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can b

feat(stm32mp1): introduce new flag for STM32MP13

STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can be used as monitor.
STM32MP13 uses the header v2.0 format for stm32image generation
for BL2.

Change-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st): update stm32image tool for header v2

The stm32image tool is updated to manage new header v2.0 for BL2
images.
Add new structure for the header v2.0 management.
Adapt to keep compatibility

feat(st): update stm32image tool for header v2

The stm32image tool is updated to manage new header v2.0 for BL2
images.
Add new structure for the header v2.0 management.
Adapt to keep compatibility with v1.0.
Add the header version major and minor in the command line
when executing the tool, as well as binary type (0x10 for BL2).

Change-Id: I70c187e8e7e95b57ab7cfad63df314307a78f1d6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Merge changes from topic "spectre_bhb" into integration

* changes:
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
fix(security): workaround for CVE-2022-23960 for Cortex-A57, Co

Merge changes from topic "spectre_bhb" into integration

* changes:
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72
fix(fvp): disable reclaiming init code by default

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