1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool is_full_reconfig; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else 67 args[2] = bytes_per_block; 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) 85 break; 86 return 0; 87 } 88 89 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 90 { 91 uint32_t ret; 92 93 if (query_type == 1) 94 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 95 else 96 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 97 98 if (ret) { 99 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 100 return INTEL_SIP_SMC_STATUS_BUSY; 101 else 102 return INTEL_SIP_SMC_STATUS_ERROR; 103 } 104 105 if (query_type != 1) { 106 /* full reconfiguration */ 107 if (is_full_reconfig) 108 socfpga_bridges_enable(); /* Enable bridge */ 109 } 110 111 return INTEL_SIP_SMC_STATUS_OK; 112 } 113 114 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 115 { 116 int i; 117 118 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 119 if (fpga_config_buffers[i].block_number == current_block) { 120 fpga_config_buffers[i].subblocks_sent--; 121 if (fpga_config_buffers[i].subblocks_sent == 0 122 && fpga_config_buffers[i].size <= 123 fpga_config_buffers[i].size_written) { 124 fpga_config_buffers[i].write_requested = 0; 125 current_block++; 126 *buffer_addr_completed = 127 fpga_config_buffers[i].addr; 128 return 0; 129 } 130 } 131 } 132 133 return -1; 134 } 135 136 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 137 uint32_t *count, uint32_t *job_id) 138 { 139 uint32_t resp[5]; 140 unsigned int resp_len = ARRAY_SIZE(resp); 141 int status = INTEL_SIP_SMC_STATUS_OK; 142 int all_completed = 1; 143 *count = 0; 144 145 while (*count < 3) { 146 147 status = mailbox_read_response(job_id, 148 resp, &resp_len); 149 150 if (status < 0) { 151 break; 152 } 153 154 max_blocks++; 155 156 if (mark_last_buffer_xfer_completed( 157 &completed_addr[*count]) == 0) { 158 *count = *count + 1; 159 } else { 160 break; 161 } 162 } 163 164 if (*count <= 0) { 165 if (status != MBOX_NO_RESPONSE && 166 status != MBOX_TIMEOUT && resp_len != 0) { 167 mailbox_clear_response(); 168 return INTEL_SIP_SMC_STATUS_ERROR; 169 } 170 171 *count = 0; 172 } 173 174 intel_fpga_sdm_write_all(); 175 176 if (*count > 0) 177 status = INTEL_SIP_SMC_STATUS_OK; 178 else if (*count == 0) 179 status = INTEL_SIP_SMC_STATUS_BUSY; 180 181 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 182 if (fpga_config_buffers[i].write_requested != 0) { 183 all_completed = 0; 184 break; 185 } 186 } 187 188 if (all_completed == 1) 189 return INTEL_SIP_SMC_STATUS_OK; 190 191 return status; 192 } 193 194 static int intel_fpga_config_start(uint32_t type) 195 { 196 uint32_t argument = 0x1; 197 uint32_t response[3]; 198 int status = 0; 199 unsigned int size = 0; 200 unsigned int resp_len = ARRAY_SIZE(response); 201 202 if ((config_type)type == FULL_CONFIG) { 203 is_full_reconfig = true; 204 } 205 206 mailbox_clear_response(); 207 208 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 209 CMD_CASUAL, NULL, NULL); 210 211 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 212 CMD_CASUAL, response, &resp_len); 213 214 if (status < 0) 215 return status; 216 217 max_blocks = response[0]; 218 bytes_per_block = response[1]; 219 220 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 221 fpga_config_buffers[i].size = 0; 222 fpga_config_buffers[i].size_written = 0; 223 fpga_config_buffers[i].addr = 0; 224 fpga_config_buffers[i].write_requested = 0; 225 fpga_config_buffers[i].block_number = 0; 226 fpga_config_buffers[i].subblocks_sent = 0; 227 } 228 229 blocks_submitted = 0; 230 current_block = 0; 231 read_block = 0; 232 current_buffer = 0; 233 234 /* full reconfiguration */ 235 if (is_full_reconfig) { 236 /* Disable bridge */ 237 socfpga_bridges_disable(); 238 } 239 240 return 0; 241 } 242 243 static bool is_fpga_config_buffer_full(void) 244 { 245 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 246 if (!fpga_config_buffers[i].write_requested) 247 return false; 248 return true; 249 } 250 251 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 252 { 253 if (!addr && !size) { 254 return true; 255 } 256 if (size > (UINT64_MAX - addr)) 257 return false; 258 if (addr < BL31_LIMIT) 259 return false; 260 if (addr + size > DRAM_BASE + DRAM_SIZE) 261 return false; 262 263 return true; 264 } 265 266 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 267 { 268 int i; 269 270 intel_fpga_sdm_write_all(); 271 272 if (!is_address_in_ddr_range(mem, size) || 273 is_fpga_config_buffer_full()) 274 return INTEL_SIP_SMC_STATUS_REJECTED; 275 276 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 277 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 278 279 if (!fpga_config_buffers[j].write_requested) { 280 fpga_config_buffers[j].addr = mem; 281 fpga_config_buffers[j].size = size; 282 fpga_config_buffers[j].size_written = 0; 283 fpga_config_buffers[j].write_requested = 1; 284 fpga_config_buffers[j].block_number = 285 blocks_submitted++; 286 fpga_config_buffers[j].subblocks_sent = 0; 287 break; 288 } 289 } 290 291 if (is_fpga_config_buffer_full()) 292 return INTEL_SIP_SMC_STATUS_BUSY; 293 294 return INTEL_SIP_SMC_STATUS_OK; 295 } 296 297 static int is_out_of_sec_range(uint64_t reg_addr) 298 { 299 #if DEBUG 300 return 0; 301 #endif 302 303 switch (reg_addr) { 304 case(0xF8011100): /* ECCCTRL1 */ 305 case(0xF8011104): /* ECCCTRL2 */ 306 case(0xF8011110): /* ERRINTEN */ 307 case(0xF8011114): /* ERRINTENS */ 308 case(0xF8011118): /* ERRINTENR */ 309 case(0xF801111C): /* INTMODE */ 310 case(0xF8011120): /* INTSTAT */ 311 case(0xF8011124): /* DIAGINTTEST */ 312 case(0xF801112C): /* DERRADDRA */ 313 case(0xFFD12028): /* SDMMCGRP_CTRL */ 314 case(0xFFD12044): /* EMAC0 */ 315 case(0xFFD12048): /* EMAC1 */ 316 case(0xFFD1204C): /* EMAC2 */ 317 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 318 case(0xFFD12094): /* ECC_INT_MASK_SET */ 319 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 320 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 321 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 322 case(0xFFD120C0): /* NOC_TIMEOUT */ 323 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 324 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 325 case(0xFFD120D0): /* NOC_IDLEACK */ 326 case(0xFFD120D4): /* NOC_IDLESTATUS */ 327 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 328 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 329 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 330 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 331 return 0; 332 333 default: 334 break; 335 } 336 337 return -1; 338 } 339 340 /* Secure register access */ 341 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 342 { 343 if (is_out_of_sec_range(reg_addr)) 344 return INTEL_SIP_SMC_STATUS_ERROR; 345 346 *retval = mmio_read_32(reg_addr); 347 348 return INTEL_SIP_SMC_STATUS_OK; 349 } 350 351 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 352 uint32_t *retval) 353 { 354 if (is_out_of_sec_range(reg_addr)) 355 return INTEL_SIP_SMC_STATUS_ERROR; 356 357 mmio_write_32(reg_addr, val); 358 359 return intel_secure_reg_read(reg_addr, retval); 360 } 361 362 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 363 uint32_t val, uint32_t *retval) 364 { 365 if (!intel_secure_reg_read(reg_addr, retval)) { 366 *retval &= ~mask; 367 *retval |= val & mask; 368 return intel_secure_reg_write(reg_addr, *retval, retval); 369 } 370 371 return INTEL_SIP_SMC_STATUS_ERROR; 372 } 373 374 /* Intel Remote System Update (RSU) services */ 375 uint64_t intel_rsu_update_address; 376 377 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 378 { 379 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 380 return INTEL_SIP_SMC_RSU_ERROR; 381 382 return INTEL_SIP_SMC_STATUS_OK; 383 } 384 385 static uint32_t intel_rsu_update(uint64_t update_address) 386 { 387 intel_rsu_update_address = update_address; 388 return INTEL_SIP_SMC_STATUS_OK; 389 } 390 391 static uint32_t intel_rsu_notify(uint32_t execution_stage) 392 { 393 if (mailbox_hps_stage_notify(execution_stage) < 0) 394 return INTEL_SIP_SMC_RSU_ERROR; 395 396 return INTEL_SIP_SMC_STATUS_OK; 397 } 398 399 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 400 uint32_t *ret_stat) 401 { 402 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 403 return INTEL_SIP_SMC_RSU_ERROR; 404 405 *ret_stat = respbuf[8]; 406 return INTEL_SIP_SMC_STATUS_OK; 407 } 408 409 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 410 uint64_t dcmf_ver_3_2) 411 { 412 rsu_dcmf_ver[0] = dcmf_ver_1_0; 413 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 414 rsu_dcmf_ver[2] = dcmf_ver_3_2; 415 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 416 417 return INTEL_SIP_SMC_STATUS_OK; 418 } 419 420 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 421 { 422 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 423 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 424 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 425 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 426 427 return INTEL_SIP_SMC_STATUS_OK; 428 } 429 430 /* Mailbox services */ 431 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 432 unsigned int len, 433 uint32_t urgent, uint32_t *response, 434 unsigned int resp_len, int *mbox_status, 435 unsigned int *len_in_resp) 436 { 437 *len_in_resp = 0; 438 *mbox_status = 0; 439 440 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 441 return INTEL_SIP_SMC_STATUS_REJECTED; 442 443 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 444 response, &resp_len); 445 446 if (status < 0) { 447 *mbox_status = -status; 448 return INTEL_SIP_SMC_STATUS_ERROR; 449 } 450 451 *mbox_status = 0; 452 *len_in_resp = resp_len; 453 return INTEL_SIP_SMC_STATUS_OK; 454 } 455 456 /* Miscellaneous HPS services */ 457 static uint32_t intel_hps_set_bridges(uint64_t enable) 458 { 459 if (enable != 0U) { 460 socfpga_bridges_enable(); 461 } else { 462 socfpga_bridges_disable(); 463 } 464 465 return INTEL_SIP_SMC_STATUS_OK; 466 } 467 468 /* 469 * This function is responsible for handling all SiP calls from the NS world 470 */ 471 472 uintptr_t sip_smc_handler(uint32_t smc_fid, 473 u_register_t x1, 474 u_register_t x2, 475 u_register_t x3, 476 u_register_t x4, 477 void *cookie, 478 void *handle, 479 u_register_t flags) 480 { 481 uint32_t retval = 0; 482 uint32_t mbox_error = 0; 483 uint32_t completed_addr[3]; 484 uint64_t retval64, rsu_respbuf[9]; 485 int status = INTEL_SIP_SMC_STATUS_OK; 486 int mbox_status; 487 unsigned int len_in_resp; 488 u_register_t x5, x6; 489 490 switch (smc_fid) { 491 case SIP_SVC_UID: 492 /* Return UID to the caller */ 493 SMC_UUID_RET(handle, intl_svc_uid); 494 495 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 496 status = intel_mailbox_fpga_config_isdone(x1); 497 SMC_RET4(handle, status, 0, 0, 0); 498 499 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 500 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 501 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 502 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 503 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 504 505 case INTEL_SIP_SMC_FPGA_CONFIG_START: 506 status = intel_fpga_config_start(x1); 507 SMC_RET4(handle, status, 0, 0, 0); 508 509 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 510 status = intel_fpga_config_write(x1, x2); 511 SMC_RET4(handle, status, 0, 0, 0); 512 513 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 514 status = intel_fpga_config_completed_write(completed_addr, 515 &retval, &rcv_id); 516 switch (retval) { 517 case 1: 518 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 519 completed_addr[0], 0, 0); 520 521 case 2: 522 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 523 completed_addr[0], 524 completed_addr[1], 0); 525 526 case 3: 527 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 528 completed_addr[0], 529 completed_addr[1], 530 completed_addr[2]); 531 532 case 0: 533 SMC_RET4(handle, status, 0, 0, 0); 534 535 default: 536 mailbox_clear_response(); 537 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 538 } 539 540 case INTEL_SIP_SMC_REG_READ: 541 status = intel_secure_reg_read(x1, &retval); 542 SMC_RET3(handle, status, retval, x1); 543 544 case INTEL_SIP_SMC_REG_WRITE: 545 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 546 SMC_RET3(handle, status, retval, x1); 547 548 case INTEL_SIP_SMC_REG_UPDATE: 549 status = intel_secure_reg_update(x1, (uint32_t)x2, 550 (uint32_t)x3, &retval); 551 SMC_RET3(handle, status, retval, x1); 552 553 case INTEL_SIP_SMC_RSU_STATUS: 554 status = intel_rsu_status(rsu_respbuf, 555 ARRAY_SIZE(rsu_respbuf)); 556 if (status) { 557 SMC_RET1(handle, status); 558 } else { 559 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 560 rsu_respbuf[2], rsu_respbuf[3]); 561 } 562 563 case INTEL_SIP_SMC_RSU_UPDATE: 564 status = intel_rsu_update(x1); 565 SMC_RET1(handle, status); 566 567 case INTEL_SIP_SMC_RSU_NOTIFY: 568 status = intel_rsu_notify(x1); 569 SMC_RET1(handle, status); 570 571 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 572 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 573 ARRAY_SIZE(rsu_respbuf), &retval); 574 if (status) { 575 SMC_RET1(handle, status); 576 } else { 577 SMC_RET2(handle, status, retval); 578 } 579 580 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 581 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 582 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 583 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 584 585 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 586 status = intel_rsu_copy_dcmf_version(x1, x2); 587 SMC_RET1(handle, status); 588 589 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 590 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 591 ((uint64_t)rsu_dcmf_stat[3] << 48) | 592 ((uint64_t)rsu_dcmf_stat[2] << 32) | 593 ((uint64_t)rsu_dcmf_stat[1] << 16) | 594 rsu_dcmf_stat[0]); 595 596 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 597 status = intel_rsu_copy_dcmf_status(x1); 598 SMC_RET1(handle, status); 599 600 case INTEL_SIP_SMC_RSU_MAX_RETRY: 601 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 602 603 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 604 rsu_max_retry = x1; 605 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 606 607 case INTEL_SIP_SMC_ECC_DBE: 608 status = intel_ecc_dbe_notification(x1); 609 SMC_RET1(handle, status); 610 611 case INTEL_SIP_SMC_MBOX_SEND_CMD: 612 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 613 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 614 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 615 (uint32_t *)x5, x6, &mbox_status, 616 &len_in_resp); 617 SMC_RET3(handle, status, mbox_status, len_in_resp); 618 619 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 620 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 621 &mbox_error); 622 SMC_RET4(handle, status, mbox_error, x1, retval64); 623 624 case INTEL_SIP_SMC_SVC_VERSION: 625 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 626 SIP_SVC_VERSION_MAJOR, 627 SIP_SVC_VERSION_MINOR); 628 629 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 630 status = intel_hps_set_bridges(x1); 631 SMC_RET1(handle, status); 632 633 default: 634 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 635 cookie, handle, flags); 636 } 637 } 638 639 DECLARE_RT_SVC( 640 socfpga_sip_svc, 641 OEN_SIP_START, 642 OEN_SIP_END, 643 SMC_TYPE_FAST, 644 NULL, 645 sip_smc_handler 646 ); 647 648 DECLARE_RT_SVC( 649 socfpga_sip_svc_std, 650 OEN_SIP_START, 651 OEN_SIP_END, 652 SMC_TYPE_YIELD, 653 NULL, 654 sip_smc_handler 655 ); 656