1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool bridge_disable; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else 67 args[2] = bytes_per_block; 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) 85 break; 86 return 0; 87 } 88 89 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 90 { 91 uint32_t ret; 92 93 if (query_type == 1) 94 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 95 else 96 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 97 98 if (ret != 0U) { 99 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 100 return INTEL_SIP_SMC_STATUS_BUSY; 101 else 102 return INTEL_SIP_SMC_STATUS_ERROR; 103 } 104 105 if (bridge_disable) { 106 socfpga_bridges_enable(); /* Enable bridge */ 107 bridge_disable = false; 108 } 109 110 return INTEL_SIP_SMC_STATUS_OK; 111 } 112 113 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 114 { 115 int i; 116 117 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 118 if (fpga_config_buffers[i].block_number == current_block) { 119 fpga_config_buffers[i].subblocks_sent--; 120 if (fpga_config_buffers[i].subblocks_sent == 0 121 && fpga_config_buffers[i].size <= 122 fpga_config_buffers[i].size_written) { 123 fpga_config_buffers[i].write_requested = 0; 124 current_block++; 125 *buffer_addr_completed = 126 fpga_config_buffers[i].addr; 127 return 0; 128 } 129 } 130 } 131 132 return -1; 133 } 134 135 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 136 uint32_t *count, uint32_t *job_id) 137 { 138 uint32_t resp[5]; 139 unsigned int resp_len = ARRAY_SIZE(resp); 140 int status = INTEL_SIP_SMC_STATUS_OK; 141 int all_completed = 1; 142 *count = 0; 143 144 while (*count < 3) { 145 146 status = mailbox_read_response(job_id, 147 resp, &resp_len); 148 149 if (status < 0) { 150 break; 151 } 152 153 max_blocks++; 154 155 if (mark_last_buffer_xfer_completed( 156 &completed_addr[*count]) == 0) { 157 *count = *count + 1; 158 } else { 159 break; 160 } 161 } 162 163 if (*count <= 0) { 164 if (status != MBOX_NO_RESPONSE && 165 status != MBOX_TIMEOUT && resp_len != 0) { 166 mailbox_clear_response(); 167 return INTEL_SIP_SMC_STATUS_ERROR; 168 } 169 170 *count = 0; 171 } 172 173 intel_fpga_sdm_write_all(); 174 175 if (*count > 0) 176 status = INTEL_SIP_SMC_STATUS_OK; 177 else if (*count == 0) 178 status = INTEL_SIP_SMC_STATUS_BUSY; 179 180 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 181 if (fpga_config_buffers[i].write_requested != 0) { 182 all_completed = 0; 183 break; 184 } 185 } 186 187 if (all_completed == 1) 188 return INTEL_SIP_SMC_STATUS_OK; 189 190 return status; 191 } 192 193 static int intel_fpga_config_start(uint32_t flag) 194 { 195 uint32_t argument = 0x1; 196 uint32_t response[3]; 197 int status = 0; 198 unsigned int size = 0; 199 unsigned int resp_len = ARRAY_SIZE(response); 200 201 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 202 bridge_disable = true; 203 } 204 205 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 206 size = 1; 207 bridge_disable = false; 208 } 209 210 mailbox_clear_response(); 211 212 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 213 CMD_CASUAL, NULL, NULL); 214 215 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 216 CMD_CASUAL, response, &resp_len); 217 218 if (status < 0) { 219 bridge_disable = false; 220 return INTEL_SIP_SMC_STATUS_ERROR; 221 } 222 223 max_blocks = response[0]; 224 bytes_per_block = response[1]; 225 226 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 227 fpga_config_buffers[i].size = 0; 228 fpga_config_buffers[i].size_written = 0; 229 fpga_config_buffers[i].addr = 0; 230 fpga_config_buffers[i].write_requested = 0; 231 fpga_config_buffers[i].block_number = 0; 232 fpga_config_buffers[i].subblocks_sent = 0; 233 } 234 235 blocks_submitted = 0; 236 current_block = 0; 237 read_block = 0; 238 current_buffer = 0; 239 240 /* Disable bridge on full reconfiguration */ 241 if (bridge_disable) { 242 socfpga_bridges_disable(); 243 } 244 245 return INTEL_SIP_SMC_STATUS_OK; 246 } 247 248 static bool is_fpga_config_buffer_full(void) 249 { 250 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 251 if (!fpga_config_buffers[i].write_requested) 252 return false; 253 return true; 254 } 255 256 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 257 { 258 if (!addr && !size) { 259 return true; 260 } 261 if (size > (UINT64_MAX - addr)) 262 return false; 263 if (addr < BL31_LIMIT) 264 return false; 265 if (addr + size > DRAM_BASE + DRAM_SIZE) 266 return false; 267 268 return true; 269 } 270 271 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 272 { 273 int i; 274 275 intel_fpga_sdm_write_all(); 276 277 if (!is_address_in_ddr_range(mem, size) || 278 is_fpga_config_buffer_full()) { 279 return INTEL_SIP_SMC_STATUS_REJECTED; 280 } 281 282 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 283 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 284 285 if (!fpga_config_buffers[j].write_requested) { 286 fpga_config_buffers[j].addr = mem; 287 fpga_config_buffers[j].size = size; 288 fpga_config_buffers[j].size_written = 0; 289 fpga_config_buffers[j].write_requested = 1; 290 fpga_config_buffers[j].block_number = 291 blocks_submitted++; 292 fpga_config_buffers[j].subblocks_sent = 0; 293 break; 294 } 295 } 296 297 if (is_fpga_config_buffer_full()) { 298 return INTEL_SIP_SMC_STATUS_BUSY; 299 } 300 301 return INTEL_SIP_SMC_STATUS_OK; 302 } 303 304 static int is_out_of_sec_range(uint64_t reg_addr) 305 { 306 #if DEBUG 307 return 0; 308 #endif 309 310 switch (reg_addr) { 311 case(0xF8011100): /* ECCCTRL1 */ 312 case(0xF8011104): /* ECCCTRL2 */ 313 case(0xF8011110): /* ERRINTEN */ 314 case(0xF8011114): /* ERRINTENS */ 315 case(0xF8011118): /* ERRINTENR */ 316 case(0xF801111C): /* INTMODE */ 317 case(0xF8011120): /* INTSTAT */ 318 case(0xF8011124): /* DIAGINTTEST */ 319 case(0xF801112C): /* DERRADDRA */ 320 case(0xFFD12028): /* SDMMCGRP_CTRL */ 321 case(0xFFD12044): /* EMAC0 */ 322 case(0xFFD12048): /* EMAC1 */ 323 case(0xFFD1204C): /* EMAC2 */ 324 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 325 case(0xFFD12094): /* ECC_INT_MASK_SET */ 326 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 327 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 328 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 329 case(0xFFD120C0): /* NOC_TIMEOUT */ 330 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 331 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 332 case(0xFFD120D0): /* NOC_IDLEACK */ 333 case(0xFFD120D4): /* NOC_IDLESTATUS */ 334 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 335 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 336 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 337 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 338 return 0; 339 340 default: 341 break; 342 } 343 344 return -1; 345 } 346 347 /* Secure register access */ 348 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 349 { 350 if (is_out_of_sec_range(reg_addr)) 351 return INTEL_SIP_SMC_STATUS_ERROR; 352 353 *retval = mmio_read_32(reg_addr); 354 355 return INTEL_SIP_SMC_STATUS_OK; 356 } 357 358 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 359 uint32_t *retval) 360 { 361 if (is_out_of_sec_range(reg_addr)) 362 return INTEL_SIP_SMC_STATUS_ERROR; 363 364 mmio_write_32(reg_addr, val); 365 366 return intel_secure_reg_read(reg_addr, retval); 367 } 368 369 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 370 uint32_t val, uint32_t *retval) 371 { 372 if (!intel_secure_reg_read(reg_addr, retval)) { 373 *retval &= ~mask; 374 *retval |= val & mask; 375 return intel_secure_reg_write(reg_addr, *retval, retval); 376 } 377 378 return INTEL_SIP_SMC_STATUS_ERROR; 379 } 380 381 /* Intel Remote System Update (RSU) services */ 382 uint64_t intel_rsu_update_address; 383 384 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 385 { 386 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 387 return INTEL_SIP_SMC_RSU_ERROR; 388 389 return INTEL_SIP_SMC_STATUS_OK; 390 } 391 392 static uint32_t intel_rsu_update(uint64_t update_address) 393 { 394 intel_rsu_update_address = update_address; 395 return INTEL_SIP_SMC_STATUS_OK; 396 } 397 398 static uint32_t intel_rsu_notify(uint32_t execution_stage) 399 { 400 if (mailbox_hps_stage_notify(execution_stage) < 0) 401 return INTEL_SIP_SMC_RSU_ERROR; 402 403 return INTEL_SIP_SMC_STATUS_OK; 404 } 405 406 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 407 uint32_t *ret_stat) 408 { 409 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 410 return INTEL_SIP_SMC_RSU_ERROR; 411 412 *ret_stat = respbuf[8]; 413 return INTEL_SIP_SMC_STATUS_OK; 414 } 415 416 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 417 uint64_t dcmf_ver_3_2) 418 { 419 rsu_dcmf_ver[0] = dcmf_ver_1_0; 420 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 421 rsu_dcmf_ver[2] = dcmf_ver_3_2; 422 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 423 424 return INTEL_SIP_SMC_STATUS_OK; 425 } 426 427 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 428 { 429 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 430 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 431 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 432 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 433 434 return INTEL_SIP_SMC_STATUS_OK; 435 } 436 437 /* Mailbox services */ 438 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 439 unsigned int len, 440 uint32_t urgent, uint32_t *response, 441 unsigned int resp_len, int *mbox_status, 442 unsigned int *len_in_resp) 443 { 444 *len_in_resp = 0; 445 *mbox_status = 0; 446 447 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 448 return INTEL_SIP_SMC_STATUS_REJECTED; 449 450 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 451 response, &resp_len); 452 453 if (status < 0) { 454 *mbox_status = -status; 455 return INTEL_SIP_SMC_STATUS_ERROR; 456 } 457 458 *mbox_status = 0; 459 *len_in_resp = resp_len; 460 return INTEL_SIP_SMC_STATUS_OK; 461 } 462 463 /* Miscellaneous HPS services */ 464 static uint32_t intel_hps_set_bridges(uint64_t enable) 465 { 466 if (enable != 0U) { 467 socfpga_bridges_enable(); 468 } else { 469 socfpga_bridges_disable(); 470 } 471 472 return INTEL_SIP_SMC_STATUS_OK; 473 } 474 475 /* 476 * This function is responsible for handling all SiP calls from the NS world 477 */ 478 479 uintptr_t sip_smc_handler(uint32_t smc_fid, 480 u_register_t x1, 481 u_register_t x2, 482 u_register_t x3, 483 u_register_t x4, 484 void *cookie, 485 void *handle, 486 u_register_t flags) 487 { 488 uint32_t retval = 0; 489 uint32_t mbox_error = 0; 490 uint32_t completed_addr[3]; 491 uint64_t retval64, rsu_respbuf[9]; 492 int status = INTEL_SIP_SMC_STATUS_OK; 493 int mbox_status; 494 unsigned int len_in_resp; 495 u_register_t x5, x6; 496 497 switch (smc_fid) { 498 case SIP_SVC_UID: 499 /* Return UID to the caller */ 500 SMC_UUID_RET(handle, intl_svc_uid); 501 502 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 503 status = intel_mailbox_fpga_config_isdone(x1); 504 SMC_RET4(handle, status, 0, 0, 0); 505 506 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 507 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 508 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 509 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 510 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 511 512 case INTEL_SIP_SMC_FPGA_CONFIG_START: 513 status = intel_fpga_config_start(x1); 514 SMC_RET4(handle, status, 0, 0, 0); 515 516 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 517 status = intel_fpga_config_write(x1, x2); 518 SMC_RET4(handle, status, 0, 0, 0); 519 520 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 521 status = intel_fpga_config_completed_write(completed_addr, 522 &retval, &rcv_id); 523 switch (retval) { 524 case 1: 525 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 526 completed_addr[0], 0, 0); 527 528 case 2: 529 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 530 completed_addr[0], 531 completed_addr[1], 0); 532 533 case 3: 534 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 535 completed_addr[0], 536 completed_addr[1], 537 completed_addr[2]); 538 539 case 0: 540 SMC_RET4(handle, status, 0, 0, 0); 541 542 default: 543 mailbox_clear_response(); 544 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 545 } 546 547 case INTEL_SIP_SMC_REG_READ: 548 status = intel_secure_reg_read(x1, &retval); 549 SMC_RET3(handle, status, retval, x1); 550 551 case INTEL_SIP_SMC_REG_WRITE: 552 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 553 SMC_RET3(handle, status, retval, x1); 554 555 case INTEL_SIP_SMC_REG_UPDATE: 556 status = intel_secure_reg_update(x1, (uint32_t)x2, 557 (uint32_t)x3, &retval); 558 SMC_RET3(handle, status, retval, x1); 559 560 case INTEL_SIP_SMC_RSU_STATUS: 561 status = intel_rsu_status(rsu_respbuf, 562 ARRAY_SIZE(rsu_respbuf)); 563 if (status) { 564 SMC_RET1(handle, status); 565 } else { 566 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 567 rsu_respbuf[2], rsu_respbuf[3]); 568 } 569 570 case INTEL_SIP_SMC_RSU_UPDATE: 571 status = intel_rsu_update(x1); 572 SMC_RET1(handle, status); 573 574 case INTEL_SIP_SMC_RSU_NOTIFY: 575 status = intel_rsu_notify(x1); 576 SMC_RET1(handle, status); 577 578 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 579 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 580 ARRAY_SIZE(rsu_respbuf), &retval); 581 if (status) { 582 SMC_RET1(handle, status); 583 } else { 584 SMC_RET2(handle, status, retval); 585 } 586 587 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 588 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 589 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 590 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 591 592 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 593 status = intel_rsu_copy_dcmf_version(x1, x2); 594 SMC_RET1(handle, status); 595 596 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 597 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 598 ((uint64_t)rsu_dcmf_stat[3] << 48) | 599 ((uint64_t)rsu_dcmf_stat[2] << 32) | 600 ((uint64_t)rsu_dcmf_stat[1] << 16) | 601 rsu_dcmf_stat[0]); 602 603 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 604 status = intel_rsu_copy_dcmf_status(x1); 605 SMC_RET1(handle, status); 606 607 case INTEL_SIP_SMC_RSU_MAX_RETRY: 608 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 609 610 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 611 rsu_max_retry = x1; 612 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 613 614 case INTEL_SIP_SMC_ECC_DBE: 615 status = intel_ecc_dbe_notification(x1); 616 SMC_RET1(handle, status); 617 618 case INTEL_SIP_SMC_MBOX_SEND_CMD: 619 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 620 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 621 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 622 (uint32_t *)x5, x6, &mbox_status, 623 &len_in_resp); 624 SMC_RET3(handle, status, mbox_status, len_in_resp); 625 626 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 627 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 628 &mbox_error); 629 SMC_RET4(handle, status, mbox_error, x1, retval64); 630 631 case INTEL_SIP_SMC_SVC_VERSION: 632 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 633 SIP_SVC_VERSION_MAJOR, 634 SIP_SVC_VERSION_MINOR); 635 636 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 637 status = intel_hps_set_bridges(x1); 638 SMC_RET1(handle, status); 639 640 default: 641 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 642 cookie, handle, flags); 643 } 644 } 645 646 DECLARE_RT_SVC( 647 socfpga_sip_svc, 648 OEN_SIP_START, 649 OEN_SIP_END, 650 SMC_TYPE_FAST, 651 NULL, 652 sip_smc_handler 653 ); 654 655 DECLARE_RT_SVC( 656 socfpga_sip_svc_std, 657 OEN_SIP_START, 658 OEN_SIP_END, 659 SMC_TYPE_YIELD, 660 NULL, 661 sip_smc_handler 662 ); 663