1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool is_full_reconfig; 27 28 29 /* SiP Service UUID */ 30 DEFINE_SVC_UUID2(intl_svc_uid, 31 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 32 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 33 34 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 35 uint64_t x1, 36 uint64_t x2, 37 uint64_t x3, 38 uint64_t x4, 39 void *cookie, 40 void *handle, 41 uint64_t flags) 42 { 43 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 44 SMC_RET1(handle, SMC_UNK); 45 } 46 47 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 48 49 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 50 { 51 uint32_t args[3]; 52 53 while (max_blocks > 0 && buffer->size > buffer->size_written) { 54 args[0] = (1<<8); 55 args[1] = buffer->addr + buffer->size_written; 56 if (buffer->size - buffer->size_written <= bytes_per_block) { 57 args[2] = buffer->size - buffer->size_written; 58 current_buffer++; 59 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 60 } else 61 args[2] = bytes_per_block; 62 63 buffer->size_written += args[2]; 64 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 65 3U, CMD_INDIRECT); 66 67 buffer->subblocks_sent++; 68 max_blocks--; 69 } 70 71 return !max_blocks; 72 } 73 74 static int intel_fpga_sdm_write_all(void) 75 { 76 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 77 if (intel_fpga_sdm_write_buffer( 78 &fpga_config_buffers[current_buffer])) 79 break; 80 return 0; 81 } 82 83 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 84 { 85 uint32_t ret; 86 87 if (query_type == 1) 88 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 89 else 90 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 91 92 if (ret) { 93 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 94 return INTEL_SIP_SMC_STATUS_BUSY; 95 else 96 return INTEL_SIP_SMC_STATUS_ERROR; 97 } 98 99 if (query_type != 1) { 100 /* full reconfiguration */ 101 if (is_full_reconfig) 102 socfpga_bridges_enable(); /* Enable bridge */ 103 } 104 105 return INTEL_SIP_SMC_STATUS_OK; 106 } 107 108 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 109 { 110 int i; 111 112 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 113 if (fpga_config_buffers[i].block_number == current_block) { 114 fpga_config_buffers[i].subblocks_sent--; 115 if (fpga_config_buffers[i].subblocks_sent == 0 116 && fpga_config_buffers[i].size <= 117 fpga_config_buffers[i].size_written) { 118 fpga_config_buffers[i].write_requested = 0; 119 current_block++; 120 *buffer_addr_completed = 121 fpga_config_buffers[i].addr; 122 return 0; 123 } 124 } 125 } 126 127 return -1; 128 } 129 130 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 131 uint32_t *count, uint32_t *job_id) 132 { 133 uint32_t resp[5]; 134 unsigned int resp_len = ARRAY_SIZE(resp); 135 int status = INTEL_SIP_SMC_STATUS_OK; 136 int all_completed = 1; 137 *count = 0; 138 139 while (*count < 3) { 140 141 status = mailbox_read_response(job_id, 142 resp, &resp_len); 143 144 if (status < 0) { 145 break; 146 } 147 148 max_blocks++; 149 150 if (mark_last_buffer_xfer_completed( 151 &completed_addr[*count]) == 0) { 152 *count = *count + 1; 153 } else { 154 break; 155 } 156 } 157 158 if (*count <= 0) { 159 if (status != MBOX_NO_RESPONSE && 160 status != MBOX_TIMEOUT && resp_len != 0) { 161 mailbox_clear_response(); 162 return INTEL_SIP_SMC_STATUS_ERROR; 163 } 164 165 *count = 0; 166 } 167 168 intel_fpga_sdm_write_all(); 169 170 if (*count > 0) 171 status = INTEL_SIP_SMC_STATUS_OK; 172 else if (*count == 0) 173 status = INTEL_SIP_SMC_STATUS_BUSY; 174 175 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 176 if (fpga_config_buffers[i].write_requested != 0) { 177 all_completed = 0; 178 break; 179 } 180 } 181 182 if (all_completed == 1) 183 return INTEL_SIP_SMC_STATUS_OK; 184 185 return status; 186 } 187 188 static int intel_fpga_config_start(uint32_t type) 189 { 190 uint32_t argument = 0x1; 191 uint32_t response[3]; 192 int status = 0; 193 unsigned int size = 0; 194 unsigned int resp_len = ARRAY_SIZE(response); 195 196 if ((config_type)type == FULL_CONFIG) { 197 is_full_reconfig = true; 198 } 199 200 mailbox_clear_response(); 201 202 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 203 CMD_CASUAL, NULL, NULL); 204 205 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 206 CMD_CASUAL, response, &resp_len); 207 208 if (status < 0) 209 return status; 210 211 max_blocks = response[0]; 212 bytes_per_block = response[1]; 213 214 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 215 fpga_config_buffers[i].size = 0; 216 fpga_config_buffers[i].size_written = 0; 217 fpga_config_buffers[i].addr = 0; 218 fpga_config_buffers[i].write_requested = 0; 219 fpga_config_buffers[i].block_number = 0; 220 fpga_config_buffers[i].subblocks_sent = 0; 221 } 222 223 blocks_submitted = 0; 224 current_block = 0; 225 read_block = 0; 226 current_buffer = 0; 227 228 /* full reconfiguration */ 229 if (is_full_reconfig) { 230 /* Disable bridge */ 231 socfpga_bridges_disable(); 232 } 233 234 return 0; 235 } 236 237 static bool is_fpga_config_buffer_full(void) 238 { 239 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 240 if (!fpga_config_buffers[i].write_requested) 241 return false; 242 return true; 243 } 244 245 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 246 { 247 if (!addr && !size) { 248 return true; 249 } 250 if (size > (UINT64_MAX - addr)) 251 return false; 252 if (addr < BL31_LIMIT) 253 return false; 254 if (addr + size > DRAM_BASE + DRAM_SIZE) 255 return false; 256 257 return true; 258 } 259 260 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 261 { 262 int i; 263 264 intel_fpga_sdm_write_all(); 265 266 if (!is_address_in_ddr_range(mem, size) || 267 is_fpga_config_buffer_full()) 268 return INTEL_SIP_SMC_STATUS_REJECTED; 269 270 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 271 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 272 273 if (!fpga_config_buffers[j].write_requested) { 274 fpga_config_buffers[j].addr = mem; 275 fpga_config_buffers[j].size = size; 276 fpga_config_buffers[j].size_written = 0; 277 fpga_config_buffers[j].write_requested = 1; 278 fpga_config_buffers[j].block_number = 279 blocks_submitted++; 280 fpga_config_buffers[j].subblocks_sent = 0; 281 break; 282 } 283 } 284 285 if (is_fpga_config_buffer_full()) 286 return INTEL_SIP_SMC_STATUS_BUSY; 287 288 return INTEL_SIP_SMC_STATUS_OK; 289 } 290 291 static int is_out_of_sec_range(uint64_t reg_addr) 292 { 293 #if DEBUG 294 return 0; 295 #endif 296 297 switch (reg_addr) { 298 case(0xF8011100): /* ECCCTRL1 */ 299 case(0xF8011104): /* ECCCTRL2 */ 300 case(0xF8011110): /* ERRINTEN */ 301 case(0xF8011114): /* ERRINTENS */ 302 case(0xF8011118): /* ERRINTENR */ 303 case(0xF801111C): /* INTMODE */ 304 case(0xF8011120): /* INTSTAT */ 305 case(0xF8011124): /* DIAGINTTEST */ 306 case(0xF801112C): /* DERRADDRA */ 307 case(0xFFD12028): /* SDMMCGRP_CTRL */ 308 case(0xFFD12044): /* EMAC0 */ 309 case(0xFFD12048): /* EMAC1 */ 310 case(0xFFD1204C): /* EMAC2 */ 311 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 312 case(0xFFD12094): /* ECC_INT_MASK_SET */ 313 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 314 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 315 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 316 case(0xFFD120C0): /* NOC_TIMEOUT */ 317 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 318 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 319 case(0xFFD120D0): /* NOC_IDLEACK */ 320 case(0xFFD120D4): /* NOC_IDLESTATUS */ 321 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 322 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 323 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 324 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 325 return 0; 326 327 default: 328 break; 329 } 330 331 return -1; 332 } 333 334 /* Secure register access */ 335 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 336 { 337 if (is_out_of_sec_range(reg_addr)) 338 return INTEL_SIP_SMC_STATUS_ERROR; 339 340 *retval = mmio_read_32(reg_addr); 341 342 return INTEL_SIP_SMC_STATUS_OK; 343 } 344 345 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 346 uint32_t *retval) 347 { 348 if (is_out_of_sec_range(reg_addr)) 349 return INTEL_SIP_SMC_STATUS_ERROR; 350 351 mmio_write_32(reg_addr, val); 352 353 return intel_secure_reg_read(reg_addr, retval); 354 } 355 356 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 357 uint32_t val, uint32_t *retval) 358 { 359 if (!intel_secure_reg_read(reg_addr, retval)) { 360 *retval &= ~mask; 361 *retval |= val & mask; 362 return intel_secure_reg_write(reg_addr, *retval, retval); 363 } 364 365 return INTEL_SIP_SMC_STATUS_ERROR; 366 } 367 368 /* Intel Remote System Update (RSU) services */ 369 uint64_t intel_rsu_update_address; 370 371 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 372 { 373 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 374 return INTEL_SIP_SMC_RSU_ERROR; 375 376 return INTEL_SIP_SMC_STATUS_OK; 377 } 378 379 static uint32_t intel_rsu_update(uint64_t update_address) 380 { 381 intel_rsu_update_address = update_address; 382 return INTEL_SIP_SMC_STATUS_OK; 383 } 384 385 static uint32_t intel_rsu_notify(uint32_t execution_stage) 386 { 387 if (mailbox_hps_stage_notify(execution_stage) < 0) 388 return INTEL_SIP_SMC_RSU_ERROR; 389 390 return INTEL_SIP_SMC_STATUS_OK; 391 } 392 393 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 394 uint32_t *ret_stat) 395 { 396 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 397 return INTEL_SIP_SMC_RSU_ERROR; 398 399 *ret_stat = respbuf[8]; 400 return INTEL_SIP_SMC_STATUS_OK; 401 } 402 403 /* Mailbox services */ 404 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 405 unsigned int len, 406 uint32_t urgent, uint32_t *response, 407 unsigned int resp_len, int *mbox_status, 408 unsigned int *len_in_resp) 409 { 410 *len_in_resp = 0; 411 *mbox_status = 0; 412 413 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 414 return INTEL_SIP_SMC_STATUS_REJECTED; 415 416 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 417 response, &resp_len); 418 419 if (status < 0) { 420 *mbox_status = -status; 421 return INTEL_SIP_SMC_STATUS_ERROR; 422 } 423 424 *mbox_status = 0; 425 *len_in_resp = resp_len; 426 return INTEL_SIP_SMC_STATUS_OK; 427 } 428 429 /* 430 * This function is responsible for handling all SiP calls from the NS world 431 */ 432 433 uintptr_t sip_smc_handler(uint32_t smc_fid, 434 u_register_t x1, 435 u_register_t x2, 436 u_register_t x3, 437 u_register_t x4, 438 void *cookie, 439 void *handle, 440 u_register_t flags) 441 { 442 uint32_t retval = 0; 443 uint32_t mbox_error = 0; 444 uint32_t completed_addr[3]; 445 uint64_t retval64, rsu_respbuf[9]; 446 int status = INTEL_SIP_SMC_STATUS_OK; 447 int mbox_status; 448 unsigned int len_in_resp; 449 u_register_t x5, x6; 450 451 switch (smc_fid) { 452 case SIP_SVC_UID: 453 /* Return UID to the caller */ 454 SMC_UUID_RET(handle, intl_svc_uid); 455 456 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 457 status = intel_mailbox_fpga_config_isdone(x1); 458 SMC_RET4(handle, status, 0, 0, 0); 459 460 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 461 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 462 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 463 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 464 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 465 466 case INTEL_SIP_SMC_FPGA_CONFIG_START: 467 status = intel_fpga_config_start(x1); 468 SMC_RET4(handle, status, 0, 0, 0); 469 470 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 471 status = intel_fpga_config_write(x1, x2); 472 SMC_RET4(handle, status, 0, 0, 0); 473 474 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 475 status = intel_fpga_config_completed_write(completed_addr, 476 &retval, &rcv_id); 477 switch (retval) { 478 case 1: 479 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 480 completed_addr[0], 0, 0); 481 482 case 2: 483 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 484 completed_addr[0], 485 completed_addr[1], 0); 486 487 case 3: 488 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 489 completed_addr[0], 490 completed_addr[1], 491 completed_addr[2]); 492 493 case 0: 494 SMC_RET4(handle, status, 0, 0, 0); 495 496 default: 497 mailbox_clear_response(); 498 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 499 } 500 501 case INTEL_SIP_SMC_REG_READ: 502 status = intel_secure_reg_read(x1, &retval); 503 SMC_RET3(handle, status, retval, x1); 504 505 case INTEL_SIP_SMC_REG_WRITE: 506 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 507 SMC_RET3(handle, status, retval, x1); 508 509 case INTEL_SIP_SMC_REG_UPDATE: 510 status = intel_secure_reg_update(x1, (uint32_t)x2, 511 (uint32_t)x3, &retval); 512 SMC_RET3(handle, status, retval, x1); 513 514 case INTEL_SIP_SMC_RSU_STATUS: 515 status = intel_rsu_status(rsu_respbuf, 516 ARRAY_SIZE(rsu_respbuf)); 517 if (status) { 518 SMC_RET1(handle, status); 519 } else { 520 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 521 rsu_respbuf[2], rsu_respbuf[3]); 522 } 523 524 case INTEL_SIP_SMC_RSU_UPDATE: 525 status = intel_rsu_update(x1); 526 SMC_RET1(handle, status); 527 528 case INTEL_SIP_SMC_RSU_NOTIFY: 529 status = intel_rsu_notify(x1); 530 SMC_RET1(handle, status); 531 532 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 533 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 534 ARRAY_SIZE(rsu_respbuf), &retval); 535 if (status) { 536 SMC_RET1(handle, status); 537 } else { 538 SMC_RET2(handle, status, retval); 539 } 540 541 case INTEL_SIP_SMC_ECC_DBE: 542 status = intel_ecc_dbe_notification(x1); 543 SMC_RET1(handle, status); 544 545 case INTEL_SIP_SMC_MBOX_SEND_CMD: 546 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 547 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 548 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 549 (uint32_t *)x5, x6, &mbox_status, 550 &len_in_resp); 551 SMC_RET3(handle, status, mbox_status, len_in_resp); 552 553 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 554 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 555 &mbox_error); 556 SMC_RET4(handle, status, mbox_error, x1, retval64); 557 558 case INTEL_SIP_SMC_SVC_VERSION: 559 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 560 SIP_SVC_VERSION_MAJOR, 561 SIP_SVC_VERSION_MINOR); 562 563 default: 564 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 565 cookie, handle, flags); 566 } 567 } 568 569 DECLARE_RT_SVC( 570 socfpga_sip_svc, 571 OEN_SIP_START, 572 OEN_SIP_END, 573 SMC_TYPE_FAST, 574 NULL, 575 sip_smc_handler 576 ); 577 578 DECLARE_RT_SVC( 579 socfpga_sip_svc_std, 580 OEN_SIP_START, 581 OEN_SIP_END, 582 SMC_TYPE_YIELD, 583 NULL, 584 sip_smc_handler 585 ); 586