1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool is_full_reconfig; 27 28 /* RSU DCMF version */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 34 /* SiP Service UUID */ 35 DEFINE_SVC_UUID2(intl_svc_uid, 36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 38 39 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 49 SMC_RET1(handle, SMC_UNK); 50 } 51 52 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 53 54 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 55 { 56 uint32_t args[3]; 57 58 while (max_blocks > 0 && buffer->size > buffer->size_written) { 59 args[0] = (1<<8); 60 args[1] = buffer->addr + buffer->size_written; 61 if (buffer->size - buffer->size_written <= bytes_per_block) { 62 args[2] = buffer->size - buffer->size_written; 63 current_buffer++; 64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 65 } else 66 args[2] = bytes_per_block; 67 68 buffer->size_written += args[2]; 69 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 70 3U, CMD_INDIRECT); 71 72 buffer->subblocks_sent++; 73 max_blocks--; 74 } 75 76 return !max_blocks; 77 } 78 79 static int intel_fpga_sdm_write_all(void) 80 { 81 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 82 if (intel_fpga_sdm_write_buffer( 83 &fpga_config_buffers[current_buffer])) 84 break; 85 return 0; 86 } 87 88 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 89 { 90 uint32_t ret; 91 92 if (query_type == 1) 93 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 94 else 95 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 96 97 if (ret) { 98 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 99 return INTEL_SIP_SMC_STATUS_BUSY; 100 else 101 return INTEL_SIP_SMC_STATUS_ERROR; 102 } 103 104 if (query_type != 1) { 105 /* full reconfiguration */ 106 if (is_full_reconfig) 107 socfpga_bridges_enable(); /* Enable bridge */ 108 } 109 110 return INTEL_SIP_SMC_STATUS_OK; 111 } 112 113 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 114 { 115 int i; 116 117 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 118 if (fpga_config_buffers[i].block_number == current_block) { 119 fpga_config_buffers[i].subblocks_sent--; 120 if (fpga_config_buffers[i].subblocks_sent == 0 121 && fpga_config_buffers[i].size <= 122 fpga_config_buffers[i].size_written) { 123 fpga_config_buffers[i].write_requested = 0; 124 current_block++; 125 *buffer_addr_completed = 126 fpga_config_buffers[i].addr; 127 return 0; 128 } 129 } 130 } 131 132 return -1; 133 } 134 135 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 136 uint32_t *count, uint32_t *job_id) 137 { 138 uint32_t resp[5]; 139 unsigned int resp_len = ARRAY_SIZE(resp); 140 int status = INTEL_SIP_SMC_STATUS_OK; 141 int all_completed = 1; 142 *count = 0; 143 144 while (*count < 3) { 145 146 status = mailbox_read_response(job_id, 147 resp, &resp_len); 148 149 if (status < 0) { 150 break; 151 } 152 153 max_blocks++; 154 155 if (mark_last_buffer_xfer_completed( 156 &completed_addr[*count]) == 0) { 157 *count = *count + 1; 158 } else { 159 break; 160 } 161 } 162 163 if (*count <= 0) { 164 if (status != MBOX_NO_RESPONSE && 165 status != MBOX_TIMEOUT && resp_len != 0) { 166 mailbox_clear_response(); 167 return INTEL_SIP_SMC_STATUS_ERROR; 168 } 169 170 *count = 0; 171 } 172 173 intel_fpga_sdm_write_all(); 174 175 if (*count > 0) 176 status = INTEL_SIP_SMC_STATUS_OK; 177 else if (*count == 0) 178 status = INTEL_SIP_SMC_STATUS_BUSY; 179 180 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 181 if (fpga_config_buffers[i].write_requested != 0) { 182 all_completed = 0; 183 break; 184 } 185 } 186 187 if (all_completed == 1) 188 return INTEL_SIP_SMC_STATUS_OK; 189 190 return status; 191 } 192 193 static int intel_fpga_config_start(uint32_t type) 194 { 195 uint32_t argument = 0x1; 196 uint32_t response[3]; 197 int status = 0; 198 unsigned int size = 0; 199 unsigned int resp_len = ARRAY_SIZE(response); 200 201 if ((config_type)type == FULL_CONFIG) { 202 is_full_reconfig = true; 203 } 204 205 mailbox_clear_response(); 206 207 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 208 CMD_CASUAL, NULL, NULL); 209 210 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 211 CMD_CASUAL, response, &resp_len); 212 213 if (status < 0) 214 return status; 215 216 max_blocks = response[0]; 217 bytes_per_block = response[1]; 218 219 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 220 fpga_config_buffers[i].size = 0; 221 fpga_config_buffers[i].size_written = 0; 222 fpga_config_buffers[i].addr = 0; 223 fpga_config_buffers[i].write_requested = 0; 224 fpga_config_buffers[i].block_number = 0; 225 fpga_config_buffers[i].subblocks_sent = 0; 226 } 227 228 blocks_submitted = 0; 229 current_block = 0; 230 read_block = 0; 231 current_buffer = 0; 232 233 /* full reconfiguration */ 234 if (is_full_reconfig) { 235 /* Disable bridge */ 236 socfpga_bridges_disable(); 237 } 238 239 return 0; 240 } 241 242 static bool is_fpga_config_buffer_full(void) 243 { 244 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 245 if (!fpga_config_buffers[i].write_requested) 246 return false; 247 return true; 248 } 249 250 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 251 { 252 if (!addr && !size) { 253 return true; 254 } 255 if (size > (UINT64_MAX - addr)) 256 return false; 257 if (addr < BL31_LIMIT) 258 return false; 259 if (addr + size > DRAM_BASE + DRAM_SIZE) 260 return false; 261 262 return true; 263 } 264 265 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 266 { 267 int i; 268 269 intel_fpga_sdm_write_all(); 270 271 if (!is_address_in_ddr_range(mem, size) || 272 is_fpga_config_buffer_full()) 273 return INTEL_SIP_SMC_STATUS_REJECTED; 274 275 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 276 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 277 278 if (!fpga_config_buffers[j].write_requested) { 279 fpga_config_buffers[j].addr = mem; 280 fpga_config_buffers[j].size = size; 281 fpga_config_buffers[j].size_written = 0; 282 fpga_config_buffers[j].write_requested = 1; 283 fpga_config_buffers[j].block_number = 284 blocks_submitted++; 285 fpga_config_buffers[j].subblocks_sent = 0; 286 break; 287 } 288 } 289 290 if (is_fpga_config_buffer_full()) 291 return INTEL_SIP_SMC_STATUS_BUSY; 292 293 return INTEL_SIP_SMC_STATUS_OK; 294 } 295 296 static int is_out_of_sec_range(uint64_t reg_addr) 297 { 298 #if DEBUG 299 return 0; 300 #endif 301 302 switch (reg_addr) { 303 case(0xF8011100): /* ECCCTRL1 */ 304 case(0xF8011104): /* ECCCTRL2 */ 305 case(0xF8011110): /* ERRINTEN */ 306 case(0xF8011114): /* ERRINTENS */ 307 case(0xF8011118): /* ERRINTENR */ 308 case(0xF801111C): /* INTMODE */ 309 case(0xF8011120): /* INTSTAT */ 310 case(0xF8011124): /* DIAGINTTEST */ 311 case(0xF801112C): /* DERRADDRA */ 312 case(0xFFD12028): /* SDMMCGRP_CTRL */ 313 case(0xFFD12044): /* EMAC0 */ 314 case(0xFFD12048): /* EMAC1 */ 315 case(0xFFD1204C): /* EMAC2 */ 316 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 317 case(0xFFD12094): /* ECC_INT_MASK_SET */ 318 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 319 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 320 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 321 case(0xFFD120C0): /* NOC_TIMEOUT */ 322 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 323 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 324 case(0xFFD120D0): /* NOC_IDLEACK */ 325 case(0xFFD120D4): /* NOC_IDLESTATUS */ 326 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 327 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 328 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 329 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 330 return 0; 331 332 default: 333 break; 334 } 335 336 return -1; 337 } 338 339 /* Secure register access */ 340 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 341 { 342 if (is_out_of_sec_range(reg_addr)) 343 return INTEL_SIP_SMC_STATUS_ERROR; 344 345 *retval = mmio_read_32(reg_addr); 346 347 return INTEL_SIP_SMC_STATUS_OK; 348 } 349 350 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 351 uint32_t *retval) 352 { 353 if (is_out_of_sec_range(reg_addr)) 354 return INTEL_SIP_SMC_STATUS_ERROR; 355 356 mmio_write_32(reg_addr, val); 357 358 return intel_secure_reg_read(reg_addr, retval); 359 } 360 361 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 362 uint32_t val, uint32_t *retval) 363 { 364 if (!intel_secure_reg_read(reg_addr, retval)) { 365 *retval &= ~mask; 366 *retval |= val & mask; 367 return intel_secure_reg_write(reg_addr, *retval, retval); 368 } 369 370 return INTEL_SIP_SMC_STATUS_ERROR; 371 } 372 373 /* Intel Remote System Update (RSU) services */ 374 uint64_t intel_rsu_update_address; 375 376 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 377 { 378 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 379 return INTEL_SIP_SMC_RSU_ERROR; 380 381 return INTEL_SIP_SMC_STATUS_OK; 382 } 383 384 static uint32_t intel_rsu_update(uint64_t update_address) 385 { 386 intel_rsu_update_address = update_address; 387 return INTEL_SIP_SMC_STATUS_OK; 388 } 389 390 static uint32_t intel_rsu_notify(uint32_t execution_stage) 391 { 392 if (mailbox_hps_stage_notify(execution_stage) < 0) 393 return INTEL_SIP_SMC_RSU_ERROR; 394 395 return INTEL_SIP_SMC_STATUS_OK; 396 } 397 398 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 399 uint32_t *ret_stat) 400 { 401 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 402 return INTEL_SIP_SMC_RSU_ERROR; 403 404 *ret_stat = respbuf[8]; 405 return INTEL_SIP_SMC_STATUS_OK; 406 } 407 408 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 409 uint64_t dcmf_ver_3_2) 410 { 411 rsu_dcmf_ver[0] = dcmf_ver_1_0; 412 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 413 rsu_dcmf_ver[2] = dcmf_ver_3_2; 414 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 415 416 return INTEL_SIP_SMC_STATUS_OK; 417 } 418 419 /* Mailbox services */ 420 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 421 unsigned int len, 422 uint32_t urgent, uint32_t *response, 423 unsigned int resp_len, int *mbox_status, 424 unsigned int *len_in_resp) 425 { 426 *len_in_resp = 0; 427 *mbox_status = 0; 428 429 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 430 return INTEL_SIP_SMC_STATUS_REJECTED; 431 432 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 433 response, &resp_len); 434 435 if (status < 0) { 436 *mbox_status = -status; 437 return INTEL_SIP_SMC_STATUS_ERROR; 438 } 439 440 *mbox_status = 0; 441 *len_in_resp = resp_len; 442 return INTEL_SIP_SMC_STATUS_OK; 443 } 444 445 /* Miscellaneous HPS services */ 446 static uint32_t intel_hps_set_bridges(uint64_t enable) 447 { 448 if (enable != 0U) { 449 socfpga_bridges_enable(); 450 } else { 451 socfpga_bridges_disable(); 452 } 453 454 return INTEL_SIP_SMC_STATUS_OK; 455 } 456 457 /* 458 * This function is responsible for handling all SiP calls from the NS world 459 */ 460 461 uintptr_t sip_smc_handler(uint32_t smc_fid, 462 u_register_t x1, 463 u_register_t x2, 464 u_register_t x3, 465 u_register_t x4, 466 void *cookie, 467 void *handle, 468 u_register_t flags) 469 { 470 uint32_t retval = 0; 471 uint32_t mbox_error = 0; 472 uint32_t completed_addr[3]; 473 uint64_t retval64, rsu_respbuf[9]; 474 int status = INTEL_SIP_SMC_STATUS_OK; 475 int mbox_status; 476 unsigned int len_in_resp; 477 u_register_t x5, x6; 478 479 switch (smc_fid) { 480 case SIP_SVC_UID: 481 /* Return UID to the caller */ 482 SMC_UUID_RET(handle, intl_svc_uid); 483 484 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 485 status = intel_mailbox_fpga_config_isdone(x1); 486 SMC_RET4(handle, status, 0, 0, 0); 487 488 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 489 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 490 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 491 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 492 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 493 494 case INTEL_SIP_SMC_FPGA_CONFIG_START: 495 status = intel_fpga_config_start(x1); 496 SMC_RET4(handle, status, 0, 0, 0); 497 498 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 499 status = intel_fpga_config_write(x1, x2); 500 SMC_RET4(handle, status, 0, 0, 0); 501 502 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 503 status = intel_fpga_config_completed_write(completed_addr, 504 &retval, &rcv_id); 505 switch (retval) { 506 case 1: 507 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 508 completed_addr[0], 0, 0); 509 510 case 2: 511 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 512 completed_addr[0], 513 completed_addr[1], 0); 514 515 case 3: 516 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 517 completed_addr[0], 518 completed_addr[1], 519 completed_addr[2]); 520 521 case 0: 522 SMC_RET4(handle, status, 0, 0, 0); 523 524 default: 525 mailbox_clear_response(); 526 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 527 } 528 529 case INTEL_SIP_SMC_REG_READ: 530 status = intel_secure_reg_read(x1, &retval); 531 SMC_RET3(handle, status, retval, x1); 532 533 case INTEL_SIP_SMC_REG_WRITE: 534 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 535 SMC_RET3(handle, status, retval, x1); 536 537 case INTEL_SIP_SMC_REG_UPDATE: 538 status = intel_secure_reg_update(x1, (uint32_t)x2, 539 (uint32_t)x3, &retval); 540 SMC_RET3(handle, status, retval, x1); 541 542 case INTEL_SIP_SMC_RSU_STATUS: 543 status = intel_rsu_status(rsu_respbuf, 544 ARRAY_SIZE(rsu_respbuf)); 545 if (status) { 546 SMC_RET1(handle, status); 547 } else { 548 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 549 rsu_respbuf[2], rsu_respbuf[3]); 550 } 551 552 case INTEL_SIP_SMC_RSU_UPDATE: 553 status = intel_rsu_update(x1); 554 SMC_RET1(handle, status); 555 556 case INTEL_SIP_SMC_RSU_NOTIFY: 557 status = intel_rsu_notify(x1); 558 SMC_RET1(handle, status); 559 560 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 561 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 562 ARRAY_SIZE(rsu_respbuf), &retval); 563 if (status) { 564 SMC_RET1(handle, status); 565 } else { 566 SMC_RET2(handle, status, retval); 567 } 568 569 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 570 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 571 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 572 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 573 574 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 575 status = intel_rsu_copy_dcmf_version(x1, x2); 576 SMC_RET1(handle, status); 577 578 case INTEL_SIP_SMC_RSU_MAX_RETRY: 579 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 580 581 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 582 rsu_max_retry = x1; 583 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 584 585 case INTEL_SIP_SMC_ECC_DBE: 586 status = intel_ecc_dbe_notification(x1); 587 SMC_RET1(handle, status); 588 589 case INTEL_SIP_SMC_MBOX_SEND_CMD: 590 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 591 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 592 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 593 (uint32_t *)x5, x6, &mbox_status, 594 &len_in_resp); 595 SMC_RET3(handle, status, mbox_status, len_in_resp); 596 597 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 598 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 599 &mbox_error); 600 SMC_RET4(handle, status, mbox_error, x1, retval64); 601 602 case INTEL_SIP_SMC_SVC_VERSION: 603 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 604 SIP_SVC_VERSION_MAJOR, 605 SIP_SVC_VERSION_MINOR); 606 607 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 608 status = intel_hps_set_bridges(x1); 609 SMC_RET1(handle, status); 610 611 default: 612 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 613 cookie, handle, flags); 614 } 615 } 616 617 DECLARE_RT_SVC( 618 socfpga_sip_svc, 619 OEN_SIP_START, 620 OEN_SIP_END, 621 SMC_TYPE_FAST, 622 NULL, 623 sip_smc_handler 624 ); 625 626 DECLARE_RT_SVC( 627 socfpga_sip_svc_std, 628 OEN_SIP_START, 629 OEN_SIP_END, 630 SMC_TYPE_YIELD, 631 NULL, 632 sip_smc_handler 633 ); 634