1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool is_full_reconfig; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else 67 args[2] = bytes_per_block; 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) 85 break; 86 return 0; 87 } 88 89 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 90 { 91 uint32_t ret; 92 93 if (query_type == 1) 94 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 95 else 96 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 97 98 if (ret) { 99 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 100 return INTEL_SIP_SMC_STATUS_BUSY; 101 else 102 return INTEL_SIP_SMC_STATUS_ERROR; 103 } 104 105 if (query_type != 1) { 106 /* full reconfiguration */ 107 if (is_full_reconfig) 108 socfpga_bridges_enable(); /* Enable bridge */ 109 } 110 111 return INTEL_SIP_SMC_STATUS_OK; 112 } 113 114 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 115 { 116 int i; 117 118 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 119 if (fpga_config_buffers[i].block_number == current_block) { 120 fpga_config_buffers[i].subblocks_sent--; 121 if (fpga_config_buffers[i].subblocks_sent == 0 122 && fpga_config_buffers[i].size <= 123 fpga_config_buffers[i].size_written) { 124 fpga_config_buffers[i].write_requested = 0; 125 current_block++; 126 *buffer_addr_completed = 127 fpga_config_buffers[i].addr; 128 return 0; 129 } 130 } 131 } 132 133 return -1; 134 } 135 136 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 137 uint32_t *count, uint32_t *job_id) 138 { 139 uint32_t resp[5]; 140 unsigned int resp_len = ARRAY_SIZE(resp); 141 int status = INTEL_SIP_SMC_STATUS_OK; 142 int all_completed = 1; 143 *count = 0; 144 145 while (*count < 3) { 146 147 status = mailbox_read_response(job_id, 148 resp, &resp_len); 149 150 if (status < 0) { 151 break; 152 } 153 154 max_blocks++; 155 156 if (mark_last_buffer_xfer_completed( 157 &completed_addr[*count]) == 0) { 158 *count = *count + 1; 159 } else { 160 break; 161 } 162 } 163 164 if (*count <= 0) { 165 if (status != MBOX_NO_RESPONSE && 166 status != MBOX_TIMEOUT && resp_len != 0) { 167 mailbox_clear_response(); 168 return INTEL_SIP_SMC_STATUS_ERROR; 169 } 170 171 *count = 0; 172 } 173 174 intel_fpga_sdm_write_all(); 175 176 if (*count > 0) 177 status = INTEL_SIP_SMC_STATUS_OK; 178 else if (*count == 0) 179 status = INTEL_SIP_SMC_STATUS_BUSY; 180 181 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 182 if (fpga_config_buffers[i].write_requested != 0) { 183 all_completed = 0; 184 break; 185 } 186 } 187 188 if (all_completed == 1) 189 return INTEL_SIP_SMC_STATUS_OK; 190 191 return status; 192 } 193 194 static int intel_fpga_config_start(uint32_t type) 195 { 196 uint32_t argument = 0x1; 197 uint32_t response[3]; 198 int status = 0; 199 unsigned int size = 0; 200 unsigned int resp_len = ARRAY_SIZE(response); 201 202 if ((config_type)type == FULL_CONFIG) { 203 is_full_reconfig = true; 204 } 205 206 mailbox_clear_response(); 207 208 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 209 CMD_CASUAL, NULL, NULL); 210 211 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 212 CMD_CASUAL, response, &resp_len); 213 214 if (status < 0) { 215 return INTEL_SIP_SMC_STATUS_ERROR; 216 } 217 218 max_blocks = response[0]; 219 bytes_per_block = response[1]; 220 221 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 222 fpga_config_buffers[i].size = 0; 223 fpga_config_buffers[i].size_written = 0; 224 fpga_config_buffers[i].addr = 0; 225 fpga_config_buffers[i].write_requested = 0; 226 fpga_config_buffers[i].block_number = 0; 227 fpga_config_buffers[i].subblocks_sent = 0; 228 } 229 230 blocks_submitted = 0; 231 current_block = 0; 232 read_block = 0; 233 current_buffer = 0; 234 235 /* full reconfiguration */ 236 if (is_full_reconfig) { 237 /* Disable bridge */ 238 socfpga_bridges_disable(); 239 } 240 241 return INTEL_SIP_SMC_STATUS_OK; 242 } 243 244 static bool is_fpga_config_buffer_full(void) 245 { 246 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 247 if (!fpga_config_buffers[i].write_requested) 248 return false; 249 return true; 250 } 251 252 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 253 { 254 if (!addr && !size) { 255 return true; 256 } 257 if (size > (UINT64_MAX - addr)) 258 return false; 259 if (addr < BL31_LIMIT) 260 return false; 261 if (addr + size > DRAM_BASE + DRAM_SIZE) 262 return false; 263 264 return true; 265 } 266 267 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 268 { 269 int i; 270 271 intel_fpga_sdm_write_all(); 272 273 if (!is_address_in_ddr_range(mem, size) || 274 is_fpga_config_buffer_full()) { 275 return INTEL_SIP_SMC_STATUS_REJECTED; 276 } 277 278 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 279 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 280 281 if (!fpga_config_buffers[j].write_requested) { 282 fpga_config_buffers[j].addr = mem; 283 fpga_config_buffers[j].size = size; 284 fpga_config_buffers[j].size_written = 0; 285 fpga_config_buffers[j].write_requested = 1; 286 fpga_config_buffers[j].block_number = 287 blocks_submitted++; 288 fpga_config_buffers[j].subblocks_sent = 0; 289 break; 290 } 291 } 292 293 if (is_fpga_config_buffer_full()) { 294 return INTEL_SIP_SMC_STATUS_BUSY; 295 } 296 297 return INTEL_SIP_SMC_STATUS_OK; 298 } 299 300 static int is_out_of_sec_range(uint64_t reg_addr) 301 { 302 #if DEBUG 303 return 0; 304 #endif 305 306 switch (reg_addr) { 307 case(0xF8011100): /* ECCCTRL1 */ 308 case(0xF8011104): /* ECCCTRL2 */ 309 case(0xF8011110): /* ERRINTEN */ 310 case(0xF8011114): /* ERRINTENS */ 311 case(0xF8011118): /* ERRINTENR */ 312 case(0xF801111C): /* INTMODE */ 313 case(0xF8011120): /* INTSTAT */ 314 case(0xF8011124): /* DIAGINTTEST */ 315 case(0xF801112C): /* DERRADDRA */ 316 case(0xFFD12028): /* SDMMCGRP_CTRL */ 317 case(0xFFD12044): /* EMAC0 */ 318 case(0xFFD12048): /* EMAC1 */ 319 case(0xFFD1204C): /* EMAC2 */ 320 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 321 case(0xFFD12094): /* ECC_INT_MASK_SET */ 322 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 323 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 324 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 325 case(0xFFD120C0): /* NOC_TIMEOUT */ 326 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 327 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 328 case(0xFFD120D0): /* NOC_IDLEACK */ 329 case(0xFFD120D4): /* NOC_IDLESTATUS */ 330 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 331 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 332 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 333 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 334 return 0; 335 336 default: 337 break; 338 } 339 340 return -1; 341 } 342 343 /* Secure register access */ 344 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 345 { 346 if (is_out_of_sec_range(reg_addr)) 347 return INTEL_SIP_SMC_STATUS_ERROR; 348 349 *retval = mmio_read_32(reg_addr); 350 351 return INTEL_SIP_SMC_STATUS_OK; 352 } 353 354 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 355 uint32_t *retval) 356 { 357 if (is_out_of_sec_range(reg_addr)) 358 return INTEL_SIP_SMC_STATUS_ERROR; 359 360 mmio_write_32(reg_addr, val); 361 362 return intel_secure_reg_read(reg_addr, retval); 363 } 364 365 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 366 uint32_t val, uint32_t *retval) 367 { 368 if (!intel_secure_reg_read(reg_addr, retval)) { 369 *retval &= ~mask; 370 *retval |= val & mask; 371 return intel_secure_reg_write(reg_addr, *retval, retval); 372 } 373 374 return INTEL_SIP_SMC_STATUS_ERROR; 375 } 376 377 /* Intel Remote System Update (RSU) services */ 378 uint64_t intel_rsu_update_address; 379 380 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 381 { 382 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 383 return INTEL_SIP_SMC_RSU_ERROR; 384 385 return INTEL_SIP_SMC_STATUS_OK; 386 } 387 388 static uint32_t intel_rsu_update(uint64_t update_address) 389 { 390 intel_rsu_update_address = update_address; 391 return INTEL_SIP_SMC_STATUS_OK; 392 } 393 394 static uint32_t intel_rsu_notify(uint32_t execution_stage) 395 { 396 if (mailbox_hps_stage_notify(execution_stage) < 0) 397 return INTEL_SIP_SMC_RSU_ERROR; 398 399 return INTEL_SIP_SMC_STATUS_OK; 400 } 401 402 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 403 uint32_t *ret_stat) 404 { 405 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 406 return INTEL_SIP_SMC_RSU_ERROR; 407 408 *ret_stat = respbuf[8]; 409 return INTEL_SIP_SMC_STATUS_OK; 410 } 411 412 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 413 uint64_t dcmf_ver_3_2) 414 { 415 rsu_dcmf_ver[0] = dcmf_ver_1_0; 416 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 417 rsu_dcmf_ver[2] = dcmf_ver_3_2; 418 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 419 420 return INTEL_SIP_SMC_STATUS_OK; 421 } 422 423 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 424 { 425 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 426 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 427 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 428 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 429 430 return INTEL_SIP_SMC_STATUS_OK; 431 } 432 433 /* Mailbox services */ 434 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 435 unsigned int len, 436 uint32_t urgent, uint32_t *response, 437 unsigned int resp_len, int *mbox_status, 438 unsigned int *len_in_resp) 439 { 440 *len_in_resp = 0; 441 *mbox_status = 0; 442 443 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 444 return INTEL_SIP_SMC_STATUS_REJECTED; 445 446 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 447 response, &resp_len); 448 449 if (status < 0) { 450 *mbox_status = -status; 451 return INTEL_SIP_SMC_STATUS_ERROR; 452 } 453 454 *mbox_status = 0; 455 *len_in_resp = resp_len; 456 return INTEL_SIP_SMC_STATUS_OK; 457 } 458 459 /* Miscellaneous HPS services */ 460 static uint32_t intel_hps_set_bridges(uint64_t enable) 461 { 462 if (enable != 0U) { 463 socfpga_bridges_enable(); 464 } else { 465 socfpga_bridges_disable(); 466 } 467 468 return INTEL_SIP_SMC_STATUS_OK; 469 } 470 471 /* 472 * This function is responsible for handling all SiP calls from the NS world 473 */ 474 475 uintptr_t sip_smc_handler(uint32_t smc_fid, 476 u_register_t x1, 477 u_register_t x2, 478 u_register_t x3, 479 u_register_t x4, 480 void *cookie, 481 void *handle, 482 u_register_t flags) 483 { 484 uint32_t retval = 0; 485 uint32_t mbox_error = 0; 486 uint32_t completed_addr[3]; 487 uint64_t retval64, rsu_respbuf[9]; 488 int status = INTEL_SIP_SMC_STATUS_OK; 489 int mbox_status; 490 unsigned int len_in_resp; 491 u_register_t x5, x6; 492 493 switch (smc_fid) { 494 case SIP_SVC_UID: 495 /* Return UID to the caller */ 496 SMC_UUID_RET(handle, intl_svc_uid); 497 498 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 499 status = intel_mailbox_fpga_config_isdone(x1); 500 SMC_RET4(handle, status, 0, 0, 0); 501 502 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 503 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 504 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 505 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 506 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 507 508 case INTEL_SIP_SMC_FPGA_CONFIG_START: 509 status = intel_fpga_config_start(x1); 510 SMC_RET4(handle, status, 0, 0, 0); 511 512 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 513 status = intel_fpga_config_write(x1, x2); 514 SMC_RET4(handle, status, 0, 0, 0); 515 516 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 517 status = intel_fpga_config_completed_write(completed_addr, 518 &retval, &rcv_id); 519 switch (retval) { 520 case 1: 521 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 522 completed_addr[0], 0, 0); 523 524 case 2: 525 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 526 completed_addr[0], 527 completed_addr[1], 0); 528 529 case 3: 530 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 531 completed_addr[0], 532 completed_addr[1], 533 completed_addr[2]); 534 535 case 0: 536 SMC_RET4(handle, status, 0, 0, 0); 537 538 default: 539 mailbox_clear_response(); 540 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 541 } 542 543 case INTEL_SIP_SMC_REG_READ: 544 status = intel_secure_reg_read(x1, &retval); 545 SMC_RET3(handle, status, retval, x1); 546 547 case INTEL_SIP_SMC_REG_WRITE: 548 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 549 SMC_RET3(handle, status, retval, x1); 550 551 case INTEL_SIP_SMC_REG_UPDATE: 552 status = intel_secure_reg_update(x1, (uint32_t)x2, 553 (uint32_t)x3, &retval); 554 SMC_RET3(handle, status, retval, x1); 555 556 case INTEL_SIP_SMC_RSU_STATUS: 557 status = intel_rsu_status(rsu_respbuf, 558 ARRAY_SIZE(rsu_respbuf)); 559 if (status) { 560 SMC_RET1(handle, status); 561 } else { 562 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 563 rsu_respbuf[2], rsu_respbuf[3]); 564 } 565 566 case INTEL_SIP_SMC_RSU_UPDATE: 567 status = intel_rsu_update(x1); 568 SMC_RET1(handle, status); 569 570 case INTEL_SIP_SMC_RSU_NOTIFY: 571 status = intel_rsu_notify(x1); 572 SMC_RET1(handle, status); 573 574 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 575 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 576 ARRAY_SIZE(rsu_respbuf), &retval); 577 if (status) { 578 SMC_RET1(handle, status); 579 } else { 580 SMC_RET2(handle, status, retval); 581 } 582 583 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 584 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 585 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 586 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 587 588 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 589 status = intel_rsu_copy_dcmf_version(x1, x2); 590 SMC_RET1(handle, status); 591 592 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 593 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 594 ((uint64_t)rsu_dcmf_stat[3] << 48) | 595 ((uint64_t)rsu_dcmf_stat[2] << 32) | 596 ((uint64_t)rsu_dcmf_stat[1] << 16) | 597 rsu_dcmf_stat[0]); 598 599 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 600 status = intel_rsu_copy_dcmf_status(x1); 601 SMC_RET1(handle, status); 602 603 case INTEL_SIP_SMC_RSU_MAX_RETRY: 604 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 605 606 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 607 rsu_max_retry = x1; 608 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 609 610 case INTEL_SIP_SMC_ECC_DBE: 611 status = intel_ecc_dbe_notification(x1); 612 SMC_RET1(handle, status); 613 614 case INTEL_SIP_SMC_MBOX_SEND_CMD: 615 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 616 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 617 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 618 (uint32_t *)x5, x6, &mbox_status, 619 &len_in_resp); 620 SMC_RET3(handle, status, mbox_status, len_in_resp); 621 622 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 623 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 624 &mbox_error); 625 SMC_RET4(handle, status, mbox_error, x1, retval64); 626 627 case INTEL_SIP_SMC_SVC_VERSION: 628 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 629 SIP_SVC_VERSION_MAJOR, 630 SIP_SVC_VERSION_MINOR); 631 632 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 633 status = intel_hps_set_bridges(x1); 634 SMC_RET1(handle, status); 635 636 default: 637 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 638 cookie, handle, flags); 639 } 640 } 641 642 DECLARE_RT_SVC( 643 socfpga_sip_svc, 644 OEN_SIP_START, 645 OEN_SIP_END, 646 SMC_TYPE_FAST, 647 NULL, 648 sip_smc_handler 649 ); 650 651 DECLARE_RT_SVC( 652 socfpga_sip_svc_std, 653 OEN_SIP_START, 654 OEN_SIP_END, 655 SMC_TYPE_YIELD, 656 NULL, 657 sip_smc_handler 658 ); 659