1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_NOC_H 8 #define SOCFPGA_NOC_H 9 10 /* Macros */ 11 #define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ 12 + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) 13 14 #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ 15 + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) 16 17 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ 18 + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) 19 20 /* L3 Interconnect Register Map */ 21 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 22 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 23 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c 24 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 25 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c 26 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 27 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 28 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 29 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c 30 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 31 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 32 #define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 33 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 34 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 35 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 36 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 37 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 38 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c 39 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 40 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 41 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 42 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c 43 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 44 45 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 46 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c 47 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 48 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 49 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 50 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c 51 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 52 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c 53 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 54 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 55 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 56 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 57 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 58 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 59 #define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c 60 #define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 61 #define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 62 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c 63 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 64 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 65 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 66 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c 67 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 68 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 69 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 70 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 71 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 72 73 /* CCU NOC Register Map */ 74 75 #define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688 76 #define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628 77 78 #define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) 79 #define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) 80 81 #endif 82 83