1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static int current_block, current_buffer; 23 static int read_block, max_blocks; 24 static uint32_t send_id, rcv_id; 25 static uint32_t bytes_per_block, blocks_submitted; 26 static bool is_full_reconfig; 27 28 /* RSU static variables */ 29 static uint32_t rsu_dcmf_ver[4] = {0}; 30 31 /* RSU Max Retry */ 32 static uint32_t rsu_max_retry; 33 static uint16_t rsu_dcmf_stat[4] = {0}; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else 67 args[2] = bytes_per_block; 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) 85 break; 86 return 0; 87 } 88 89 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 90 { 91 uint32_t ret; 92 93 if (query_type == 1) 94 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); 95 else 96 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); 97 98 if (ret) { 99 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 100 return INTEL_SIP_SMC_STATUS_BUSY; 101 else 102 return INTEL_SIP_SMC_STATUS_ERROR; 103 } 104 105 if (query_type != 1) { 106 /* full reconfiguration */ 107 if (is_full_reconfig) 108 socfpga_bridges_enable(); /* Enable bridge */ 109 } 110 111 return INTEL_SIP_SMC_STATUS_OK; 112 } 113 114 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 115 { 116 int i; 117 118 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 119 if (fpga_config_buffers[i].block_number == current_block) { 120 fpga_config_buffers[i].subblocks_sent--; 121 if (fpga_config_buffers[i].subblocks_sent == 0 122 && fpga_config_buffers[i].size <= 123 fpga_config_buffers[i].size_written) { 124 fpga_config_buffers[i].write_requested = 0; 125 current_block++; 126 *buffer_addr_completed = 127 fpga_config_buffers[i].addr; 128 return 0; 129 } 130 } 131 } 132 133 return -1; 134 } 135 136 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 137 uint32_t *count, uint32_t *job_id) 138 { 139 uint32_t resp[5]; 140 unsigned int resp_len = ARRAY_SIZE(resp); 141 int status = INTEL_SIP_SMC_STATUS_OK; 142 int all_completed = 1; 143 *count = 0; 144 145 while (*count < 3) { 146 147 status = mailbox_read_response(job_id, 148 resp, &resp_len); 149 150 if (status < 0) { 151 break; 152 } 153 154 max_blocks++; 155 156 if (mark_last_buffer_xfer_completed( 157 &completed_addr[*count]) == 0) { 158 *count = *count + 1; 159 } else { 160 break; 161 } 162 } 163 164 if (*count <= 0) { 165 if (status != MBOX_NO_RESPONSE && 166 status != MBOX_TIMEOUT && resp_len != 0) { 167 mailbox_clear_response(); 168 return INTEL_SIP_SMC_STATUS_ERROR; 169 } 170 171 *count = 0; 172 } 173 174 intel_fpga_sdm_write_all(); 175 176 if (*count > 0) 177 status = INTEL_SIP_SMC_STATUS_OK; 178 else if (*count == 0) 179 status = INTEL_SIP_SMC_STATUS_BUSY; 180 181 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 182 if (fpga_config_buffers[i].write_requested != 0) { 183 all_completed = 0; 184 break; 185 } 186 } 187 188 if (all_completed == 1) 189 return INTEL_SIP_SMC_STATUS_OK; 190 191 return status; 192 } 193 194 static int intel_fpga_config_start(uint32_t type) 195 { 196 uint32_t argument = 0x1; 197 uint32_t response[3]; 198 int status = 0; 199 unsigned int size = 0; 200 unsigned int resp_len = ARRAY_SIZE(response); 201 202 if ((config_type)type == FULL_CONFIG) { 203 is_full_reconfig = true; 204 } 205 206 mailbox_clear_response(); 207 208 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 209 CMD_CASUAL, NULL, NULL); 210 211 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 212 CMD_CASUAL, response, &resp_len); 213 214 if (status < 0) 215 return status; 216 217 max_blocks = response[0]; 218 bytes_per_block = response[1]; 219 220 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 221 fpga_config_buffers[i].size = 0; 222 fpga_config_buffers[i].size_written = 0; 223 fpga_config_buffers[i].addr = 0; 224 fpga_config_buffers[i].write_requested = 0; 225 fpga_config_buffers[i].block_number = 0; 226 fpga_config_buffers[i].subblocks_sent = 0; 227 } 228 229 blocks_submitted = 0; 230 current_block = 0; 231 read_block = 0; 232 current_buffer = 0; 233 234 /* full reconfiguration */ 235 if (is_full_reconfig) { 236 /* Disable bridge */ 237 socfpga_bridges_disable(); 238 } 239 240 return 0; 241 } 242 243 static bool is_fpga_config_buffer_full(void) 244 { 245 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 246 if (!fpga_config_buffers[i].write_requested) 247 return false; 248 return true; 249 } 250 251 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 252 { 253 if (!addr && !size) { 254 return true; 255 } 256 if (size > (UINT64_MAX - addr)) 257 return false; 258 if (addr < BL31_LIMIT) 259 return false; 260 if (addr + size > DRAM_BASE + DRAM_SIZE) 261 return false; 262 263 return true; 264 } 265 266 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 267 { 268 int i; 269 270 intel_fpga_sdm_write_all(); 271 272 if (!is_address_in_ddr_range(mem, size) || 273 is_fpga_config_buffer_full()) { 274 return INTEL_SIP_SMC_STATUS_REJECTED; 275 } 276 277 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 278 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 279 280 if (!fpga_config_buffers[j].write_requested) { 281 fpga_config_buffers[j].addr = mem; 282 fpga_config_buffers[j].size = size; 283 fpga_config_buffers[j].size_written = 0; 284 fpga_config_buffers[j].write_requested = 1; 285 fpga_config_buffers[j].block_number = 286 blocks_submitted++; 287 fpga_config_buffers[j].subblocks_sent = 0; 288 break; 289 } 290 } 291 292 if (is_fpga_config_buffer_full()) { 293 return INTEL_SIP_SMC_STATUS_BUSY; 294 } 295 296 return INTEL_SIP_SMC_STATUS_OK; 297 } 298 299 static int is_out_of_sec_range(uint64_t reg_addr) 300 { 301 #if DEBUG 302 return 0; 303 #endif 304 305 switch (reg_addr) { 306 case(0xF8011100): /* ECCCTRL1 */ 307 case(0xF8011104): /* ECCCTRL2 */ 308 case(0xF8011110): /* ERRINTEN */ 309 case(0xF8011114): /* ERRINTENS */ 310 case(0xF8011118): /* ERRINTENR */ 311 case(0xF801111C): /* INTMODE */ 312 case(0xF8011120): /* INTSTAT */ 313 case(0xF8011124): /* DIAGINTTEST */ 314 case(0xF801112C): /* DERRADDRA */ 315 case(0xFFD12028): /* SDMMCGRP_CTRL */ 316 case(0xFFD12044): /* EMAC0 */ 317 case(0xFFD12048): /* EMAC1 */ 318 case(0xFFD1204C): /* EMAC2 */ 319 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 320 case(0xFFD12094): /* ECC_INT_MASK_SET */ 321 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 322 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 323 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 324 case(0xFFD120C0): /* NOC_TIMEOUT */ 325 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 326 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 327 case(0xFFD120D0): /* NOC_IDLEACK */ 328 case(0xFFD120D4): /* NOC_IDLESTATUS */ 329 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 330 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 331 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 332 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 333 return 0; 334 335 default: 336 break; 337 } 338 339 return -1; 340 } 341 342 /* Secure register access */ 343 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 344 { 345 if (is_out_of_sec_range(reg_addr)) 346 return INTEL_SIP_SMC_STATUS_ERROR; 347 348 *retval = mmio_read_32(reg_addr); 349 350 return INTEL_SIP_SMC_STATUS_OK; 351 } 352 353 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 354 uint32_t *retval) 355 { 356 if (is_out_of_sec_range(reg_addr)) 357 return INTEL_SIP_SMC_STATUS_ERROR; 358 359 mmio_write_32(reg_addr, val); 360 361 return intel_secure_reg_read(reg_addr, retval); 362 } 363 364 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 365 uint32_t val, uint32_t *retval) 366 { 367 if (!intel_secure_reg_read(reg_addr, retval)) { 368 *retval &= ~mask; 369 *retval |= val & mask; 370 return intel_secure_reg_write(reg_addr, *retval, retval); 371 } 372 373 return INTEL_SIP_SMC_STATUS_ERROR; 374 } 375 376 /* Intel Remote System Update (RSU) services */ 377 uint64_t intel_rsu_update_address; 378 379 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 380 { 381 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 382 return INTEL_SIP_SMC_RSU_ERROR; 383 384 return INTEL_SIP_SMC_STATUS_OK; 385 } 386 387 static uint32_t intel_rsu_update(uint64_t update_address) 388 { 389 intel_rsu_update_address = update_address; 390 return INTEL_SIP_SMC_STATUS_OK; 391 } 392 393 static uint32_t intel_rsu_notify(uint32_t execution_stage) 394 { 395 if (mailbox_hps_stage_notify(execution_stage) < 0) 396 return INTEL_SIP_SMC_RSU_ERROR; 397 398 return INTEL_SIP_SMC_STATUS_OK; 399 } 400 401 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 402 uint32_t *ret_stat) 403 { 404 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 405 return INTEL_SIP_SMC_RSU_ERROR; 406 407 *ret_stat = respbuf[8]; 408 return INTEL_SIP_SMC_STATUS_OK; 409 } 410 411 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 412 uint64_t dcmf_ver_3_2) 413 { 414 rsu_dcmf_ver[0] = dcmf_ver_1_0; 415 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 416 rsu_dcmf_ver[2] = dcmf_ver_3_2; 417 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 418 419 return INTEL_SIP_SMC_STATUS_OK; 420 } 421 422 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 423 { 424 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 425 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 426 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 427 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 428 429 return INTEL_SIP_SMC_STATUS_OK; 430 } 431 432 /* Mailbox services */ 433 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 434 unsigned int len, 435 uint32_t urgent, uint32_t *response, 436 unsigned int resp_len, int *mbox_status, 437 unsigned int *len_in_resp) 438 { 439 *len_in_resp = 0; 440 *mbox_status = 0; 441 442 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 443 return INTEL_SIP_SMC_STATUS_REJECTED; 444 445 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 446 response, &resp_len); 447 448 if (status < 0) { 449 *mbox_status = -status; 450 return INTEL_SIP_SMC_STATUS_ERROR; 451 } 452 453 *mbox_status = 0; 454 *len_in_resp = resp_len; 455 return INTEL_SIP_SMC_STATUS_OK; 456 } 457 458 /* Miscellaneous HPS services */ 459 static uint32_t intel_hps_set_bridges(uint64_t enable) 460 { 461 if (enable != 0U) { 462 socfpga_bridges_enable(); 463 } else { 464 socfpga_bridges_disable(); 465 } 466 467 return INTEL_SIP_SMC_STATUS_OK; 468 } 469 470 /* 471 * This function is responsible for handling all SiP calls from the NS world 472 */ 473 474 uintptr_t sip_smc_handler(uint32_t smc_fid, 475 u_register_t x1, 476 u_register_t x2, 477 u_register_t x3, 478 u_register_t x4, 479 void *cookie, 480 void *handle, 481 u_register_t flags) 482 { 483 uint32_t retval = 0; 484 uint32_t mbox_error = 0; 485 uint32_t completed_addr[3]; 486 uint64_t retval64, rsu_respbuf[9]; 487 int status = INTEL_SIP_SMC_STATUS_OK; 488 int mbox_status; 489 unsigned int len_in_resp; 490 u_register_t x5, x6; 491 492 switch (smc_fid) { 493 case SIP_SVC_UID: 494 /* Return UID to the caller */ 495 SMC_UUID_RET(handle, intl_svc_uid); 496 497 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 498 status = intel_mailbox_fpga_config_isdone(x1); 499 SMC_RET4(handle, status, 0, 0, 0); 500 501 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 502 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 503 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 504 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 505 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 506 507 case INTEL_SIP_SMC_FPGA_CONFIG_START: 508 status = intel_fpga_config_start(x1); 509 SMC_RET4(handle, status, 0, 0, 0); 510 511 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 512 status = intel_fpga_config_write(x1, x2); 513 SMC_RET4(handle, status, 0, 0, 0); 514 515 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 516 status = intel_fpga_config_completed_write(completed_addr, 517 &retval, &rcv_id); 518 switch (retval) { 519 case 1: 520 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 521 completed_addr[0], 0, 0); 522 523 case 2: 524 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 525 completed_addr[0], 526 completed_addr[1], 0); 527 528 case 3: 529 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 530 completed_addr[0], 531 completed_addr[1], 532 completed_addr[2]); 533 534 case 0: 535 SMC_RET4(handle, status, 0, 0, 0); 536 537 default: 538 mailbox_clear_response(); 539 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 540 } 541 542 case INTEL_SIP_SMC_REG_READ: 543 status = intel_secure_reg_read(x1, &retval); 544 SMC_RET3(handle, status, retval, x1); 545 546 case INTEL_SIP_SMC_REG_WRITE: 547 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 548 SMC_RET3(handle, status, retval, x1); 549 550 case INTEL_SIP_SMC_REG_UPDATE: 551 status = intel_secure_reg_update(x1, (uint32_t)x2, 552 (uint32_t)x3, &retval); 553 SMC_RET3(handle, status, retval, x1); 554 555 case INTEL_SIP_SMC_RSU_STATUS: 556 status = intel_rsu_status(rsu_respbuf, 557 ARRAY_SIZE(rsu_respbuf)); 558 if (status) { 559 SMC_RET1(handle, status); 560 } else { 561 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 562 rsu_respbuf[2], rsu_respbuf[3]); 563 } 564 565 case INTEL_SIP_SMC_RSU_UPDATE: 566 status = intel_rsu_update(x1); 567 SMC_RET1(handle, status); 568 569 case INTEL_SIP_SMC_RSU_NOTIFY: 570 status = intel_rsu_notify(x1); 571 SMC_RET1(handle, status); 572 573 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 574 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 575 ARRAY_SIZE(rsu_respbuf), &retval); 576 if (status) { 577 SMC_RET1(handle, status); 578 } else { 579 SMC_RET2(handle, status, retval); 580 } 581 582 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 583 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 584 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 585 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 586 587 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 588 status = intel_rsu_copy_dcmf_version(x1, x2); 589 SMC_RET1(handle, status); 590 591 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 592 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 593 ((uint64_t)rsu_dcmf_stat[3] << 48) | 594 ((uint64_t)rsu_dcmf_stat[2] << 32) | 595 ((uint64_t)rsu_dcmf_stat[1] << 16) | 596 rsu_dcmf_stat[0]); 597 598 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 599 status = intel_rsu_copy_dcmf_status(x1); 600 SMC_RET1(handle, status); 601 602 case INTEL_SIP_SMC_RSU_MAX_RETRY: 603 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 604 605 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 606 rsu_max_retry = x1; 607 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 608 609 case INTEL_SIP_SMC_ECC_DBE: 610 status = intel_ecc_dbe_notification(x1); 611 SMC_RET1(handle, status); 612 613 case INTEL_SIP_SMC_MBOX_SEND_CMD: 614 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 615 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 616 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 617 (uint32_t *)x5, x6, &mbox_status, 618 &len_in_resp); 619 SMC_RET3(handle, status, mbox_status, len_in_resp); 620 621 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 622 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 623 &mbox_error); 624 SMC_RET4(handle, status, mbox_error, x1, retval64); 625 626 case INTEL_SIP_SMC_SVC_VERSION: 627 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 628 SIP_SVC_VERSION_MAJOR, 629 SIP_SVC_VERSION_MINOR); 630 631 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 632 status = intel_hps_set_bridges(x1); 633 SMC_RET1(handle, status); 634 635 default: 636 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 637 cookie, handle, flags); 638 } 639 } 640 641 DECLARE_RT_SVC( 642 socfpga_sip_svc, 643 OEN_SIP_START, 644 OEN_SIP_END, 645 SMC_TYPE_FAST, 646 NULL, 647 sip_smc_handler 648 ); 649 650 DECLARE_RT_SVC( 651 socfpga_sip_svc_std, 652 OEN_SIP_START, 653 OEN_SIP_END, 654 SMC_TYPE_YIELD, 655 NULL, 656 sip_smc_handler 657 ); 658