feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_entries and create
`plat_fiptool.mk` in order to enable the integration
of the DDR FW binary into the FIP image using
`fiptool` command.

Change-Id: I10c000025378206411ab70dbc5b2e745ffb01e5d
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image

feat(s32g274a): move fip in a dedicated partition

Modify the deployment method for TF-A binaries on the SD card. To
simplify deployment, BL2 will be decorated with an IVT, making it a
bootable image, while fip.bin will be deployed as a raw MBR partition on
the SD card. This approach allows the FIP location to be auto-discovered
based on information found in the MBR. The partition ID where the image
is stored is set to partition zero but can be changed using the FIP_PART
makefile parameter. The GPT header cannot be used instead of MBR due to
the boot header on the S32G274A, which may overlap with the GPT reserved
area.

Change-Id: I26746023dba7788613a74ae69c86124b450e6bdb
Co-developed-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Co-developed-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661

feat(s32g274ardb): initialize the IO buffer

Define and initialize the IO buffer that will be used by the uSDHC
driver to load images from the SD card.

Change-Id: I8d9712b1243a58fd6830f2682edbb9e661d2f6b5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id:

feat(s32g274ardb): initialize the uSDHC driver

S32G2 and IMX share the same uSDHC controller. Therefore, it is
initialized during BL2 to facilitate the loading of subsequent boot
stages.

Change-Id: I223904c24a14a89ef676626b54a5937f39a17eda
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PS

feat(s32g274ardb): set the system counter rate

Generic timer initialization at the BL2 stage is incomplete without
configuring the system counter frequency. This configuration is
performed by the PSCI layer in BL31.

Change-Id: I134cffe47819061f1608386cf98a39014cd12396
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Cha

feat(s32g274ardb): init the generic timer for BL2

The generic timer must be initialized during BL2 because the uSDHC
driver, which will be enabled in subsequent commits, requires it for
delays.

Change-Id: Ia09b3d3565a09ace7389d2e063af1185cc80fa27
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-I

refactor(s32g274a): replace mov/movk with mov_imm

Replace pairs of mov and movk instructions with the mov_imm macro to
align with the rest of the infrastructure and avoid code duplication.

Change-Id: I3c091eb8ff111c7bc030b32ad5948cbfaea3b35c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularit

feat(s32g274a): enable MMU for BL31 stage

Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.

Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810e

feat(s32g274a): dynamically map GIC regions

Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.

Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity

feat(s32g274a): enable MMU for BL2 stage

Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.

Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off

feat(s32g274a): dynamically map siul2 and fip img

Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.

Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-of

feat(s32g274a): map each image before its loading

The regions used by the stages loaded by BL2 must be mapped before they
can be used.

Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id:

feat(s32g274a): increase the number of MMU regions

Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.

Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.

feat(s32g274a): add console mapping

Add on-demand mapping of the console registers.

Change-Id: I146af2306f167602710c57b637deb1845fd95aff
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): add ncore support

Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the fir

feat(s32g274a): add ncore support

Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.

Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d

feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d93f18e0f82bd7a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated

feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.

Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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