1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <common/desc_image_load.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 #include <plat_console.h> 16 #include <s32cc-clk-drv.h> 17 18 #include <plat_io_storage.h> 19 #include <s32cc-bl-common.h> 20 #include <s32cc-ncore.h> 21 22 #define SIUL20_BASE UL(0x4009C000) 23 #define SIUL2_PC09_MSCR UL(0x4009C2E4) 24 #define SIUL2_PC10_MSCR UL(0x4009C2E8) 25 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) 26 27 #define LIN0_TX_MSCR_CFG U(0x00214001) 28 #define LIN0_RX_MSCR_CFG U(0x00094000) 29 #define LIN0_RX_IMCR_CFG U(0x00000002) 30 31 struct bl_load_info *plat_get_bl_image_load_info(void) 32 { 33 return get_bl_load_info_from_mem_params_desc(); 34 } 35 36 struct bl_params *plat_get_next_bl_params(void) 37 { 38 return get_next_bl_params_from_mem_params_desc(); 39 } 40 41 void plat_flush_next_bl_params(void) 42 { 43 flush_bl_params_desc(); 44 } 45 46 void bl2_platform_setup(void) 47 { 48 int ret; 49 50 ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE, 51 S32G_FIP_SIZE, 52 MT_MEMORY | MT_RW | MT_SECURE); 53 if (ret != 0) { 54 panic(); 55 } 56 } 57 58 static int s32g_mmap_siul2(void) 59 { 60 return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE); 62 } 63 64 static void linflex_config_pinctrl(void) 65 { 66 /* set PC09 - MSCR[41] - for UART0 TXD */ 67 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG); 68 /* set PC10 - MSCR[42] - for UART0 RXD */ 69 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG); 70 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */ 71 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG); 72 } 73 74 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 int ret; 78 79 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which 80 * we have manually set during early BL2 boot. 81 */ 82 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU); 83 84 ncore_init(); 85 ncore_caiu_online(A53_CLUSTER0_CAIU); 86 87 ret = s32cc_init_core_clocks(); 88 if (ret != 0) { 89 panic(); 90 } 91 92 ret = s32cc_bl_mmu_setup(); 93 if (ret != 0) { 94 panic(); 95 } 96 97 ret = s32cc_init_early_clks(); 98 if (ret != 0) { 99 panic(); 100 } 101 102 ret = s32g_mmap_siul2(); 103 if (ret != 0) { 104 panic(); 105 } 106 107 generic_delay_timer_init(); 108 109 linflex_config_pinctrl(); 110 console_s32g2_register(); 111 112 plat_s32g2_io_setup(); 113 } 114 115 void bl2_el3_plat_arch_setup(void) 116 { 117 } 118 119 int bl2_plat_handle_pre_image_load(unsigned int image_id) 120 { 121 const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id); 122 const struct image_info *img_info; 123 size_t size; 124 125 if (desc == NULL) { 126 return -EINVAL; 127 } 128 129 img_info = &desc->image_info; 130 131 if ((img_info == NULL) || (img_info->image_max_size == 0U)) { 132 return -EINVAL; 133 } 134 135 size = page_align(img_info->image_max_size, UP); 136 137 return mmap_add_dynamic_region(img_info->image_base, 138 img_info->image_base, 139 size, 140 MT_MEMORY | MT_RW | MT_SECURE); 141 } 142