xref: /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c (revision 34fb2b35b9996d2afe40ad52f3a004bb90bf95f2)
1 /*
2  * Copyright 2024 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <errno.h>
8 #include <common/debug.h>
9 #include <common/desc_image_load.h>
10 #include <lib/mmio.h>
11 #include <lib/xlat_tables/xlat_tables_v2.h>
12 #include <plat/common/platform.h>
13 #include <plat_console.h>
14 #include <s32cc-clk-drv.h>
15 #include <plat_io_storage.h>
16 #include <s32cc-ncore.h>
17 
18 #define SIUL2_PC09_MSCR		UL(0x4009C2E4)
19 #define SIUL2_PC10_MSCR		UL(0x4009C2E8)
20 #define SIUL2_PC10_LIN0_IMCR	UL(0x4009CA40)
21 
22 #define LIN0_TX_MSCR_CFG	U(0x00214001)
23 #define LIN0_RX_MSCR_CFG	U(0x00094000)
24 #define LIN0_RX_IMCR_CFG	U(0x00000002)
25 
26 struct bl_load_info *plat_get_bl_image_load_info(void)
27 {
28 	return get_bl_load_info_from_mem_params_desc();
29 }
30 
31 struct bl_params *plat_get_next_bl_params(void)
32 {
33 	return get_next_bl_params_from_mem_params_desc();
34 }
35 
36 void plat_flush_next_bl_params(void)
37 {
38 	flush_bl_params_desc();
39 }
40 
41 void bl2_platform_setup(void)
42 {
43 }
44 
45 static void linflex_config_pinctrl(void)
46 {
47 	/* set PC09 - MSCR[41] - for UART0 TXD */
48 	mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
49 	/* set PC10 - MSCR[42] - for UART0 RXD */
50 	mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
51 	/* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
52 	mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
53 }
54 
55 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
56 				  u_register_t arg2, u_register_t arg3)
57 {
58 	int ret;
59 
60 	ret = s32cc_init_early_clks();
61 	if (ret != 0) {
62 		panic();
63 	}
64 
65 	linflex_config_pinctrl();
66 	console_s32g2_register();
67 
68 	/* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which
69 	 * we have manually set during early BL2 boot.
70 	 */
71 	ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU);
72 
73 	ncore_init();
74 	ncore_caiu_online(A53_CLUSTER0_CAIU);
75 
76 	plat_s32g2_io_setup();
77 }
78 
79 void bl2_el3_plat_arch_setup(void)
80 {
81 }
82 
83 int bl2_plat_handle_pre_image_load(unsigned int image_id)
84 {
85 	const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id);
86 	const struct image_info *img_info;
87 	size_t size;
88 
89 	if (desc == NULL) {
90 		return -EINVAL;
91 	}
92 
93 	img_info = &desc->image_info;
94 
95 	if ((img_info == NULL) || (img_info->image_max_size == 0U)) {
96 		return -EINVAL;
97 	}
98 
99 	size = page_align(img_info->image_max_size, UP);
100 
101 	return mmap_add_dynamic_region(img_info->image_base,
102 				       img_info->image_base,
103 				       size,
104 				       MT_MEMORY | MT_RW | MT_SECURE);
105 }
106