1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 #include <common/debug.h> 9 #include <common/desc_image_load.h> 10 #include <lib/mmio.h> 11 #include <lib/xlat_tables/xlat_tables_v2.h> 12 #include <plat/common/platform.h> 13 #include <plat_console.h> 14 #include <s32cc-clk-drv.h> 15 #include <plat_io_storage.h> 16 #include <s32cc-ncore.h> 17 18 #define SIUL20_BASE UL(0x4009C000) 19 #define SIUL2_PC09_MSCR UL(0x4009C2E4) 20 #define SIUL2_PC10_MSCR UL(0x4009C2E8) 21 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) 22 23 #define LIN0_TX_MSCR_CFG U(0x00214001) 24 #define LIN0_RX_MSCR_CFG U(0x00094000) 25 #define LIN0_RX_IMCR_CFG U(0x00000002) 26 27 struct bl_load_info *plat_get_bl_image_load_info(void) 28 { 29 return get_bl_load_info_from_mem_params_desc(); 30 } 31 32 struct bl_params *plat_get_next_bl_params(void) 33 { 34 return get_next_bl_params_from_mem_params_desc(); 35 } 36 37 void plat_flush_next_bl_params(void) 38 { 39 flush_bl_params_desc(); 40 } 41 42 void bl2_platform_setup(void) 43 { 44 int ret; 45 46 ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE, 47 S32G_FIP_SIZE, 48 MT_MEMORY | MT_RW | MT_SECURE); 49 if (ret != 0) { 50 panic(); 51 } 52 } 53 54 static int s32g_mmap_siul2(void) 55 { 56 return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE); 58 } 59 60 static void linflex_config_pinctrl(void) 61 { 62 /* set PC09 - MSCR[41] - for UART0 TXD */ 63 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG); 64 /* set PC10 - MSCR[42] - for UART0 RXD */ 65 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG); 66 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */ 67 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG); 68 } 69 70 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 71 u_register_t arg2, u_register_t arg3) 72 { 73 int ret; 74 75 /* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which 76 * we have manually set during early BL2 boot. 77 */ 78 ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU); 79 80 ncore_init(); 81 ncore_caiu_online(A53_CLUSTER0_CAIU); 82 83 ret = s32cc_init_early_clks(); 84 if (ret != 0) { 85 panic(); 86 } 87 88 ret = s32g_mmap_siul2(); 89 if (ret != 0) { 90 panic(); 91 } 92 93 linflex_config_pinctrl(); 94 console_s32g2_register(); 95 96 plat_s32g2_io_setup(); 97 } 98 99 void bl2_el3_plat_arch_setup(void) 100 { 101 } 102 103 int bl2_plat_handle_pre_image_load(unsigned int image_id) 104 { 105 const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id); 106 const struct image_info *img_info; 107 size_t size; 108 109 if (desc == NULL) { 110 return -EINVAL; 111 } 112 113 img_info = &desc->image_info; 114 115 if ((img_info == NULL) || (img_info->image_max_size == 0U)) { 116 return -EINVAL; 117 } 118 119 size = page_align(img_info->image_max_size, UP); 120 121 return mmap_add_dynamic_region(img_info->image_base, 122 img_info->image_base, 123 size, 124 MT_MEMORY | MT_RW | MT_SECURE); 125 } 126