feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add supp

feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add support to
parse and configure this DTB in BL31. NT_FW_CONFIG contains the platform
information which is needed by BL33.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib1fb5417c36523eb2ec02aa22845218de68809aa

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feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(fvp): scale SP_MIN max size based on SRAM size" into integration

Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform tok

Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform token from iat-verifier
refactor(fvp): use the example CCA platform token from iat-verifier

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Merge "refactor(rmmd): plat token requests in pieces" into integration

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token in pieces, so they fit in the shared buffer. A new
output parameter was added to the SMC call, which will return (along
with the size of bytes copied into the buffer) the number of bytes
of the token that remain to be retrieved.

TF-A will keep an offset variable that will indicate the position in
the token where the next call will retrieve bytes from. This offset
will be increased on every call by adding the number number of bytes
copied. If the received hash size is not 0, TF-A will reset the
offset to 0 and copy from that position on.

The SMC call will now return at most the size of the shared buffer
in bytes on every call. Therefore, from now on, multiple SMC calls
may be needed to be issued if the token size exceeds the shared
buffer size.

Change-Id: I591f7013d06f64e98afaf9535dbea6f815799723
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cc

refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in the FVP platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia23f0dffe618dca04f9f3c46c953a6f021101b09

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fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values,

fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values, non-secure world will see the
feature bits in the CPU ID registers and will use those registers,
triggering a panic in BL31.

Enable the feature in the optional form for the FVP build, to avoid any
panics.

Change-Id: I26ba444d784adf165db81048f93e11361c7f11ac
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to

feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to
the SRAM size used to build the FVP platform.

Change-Id: I95527e8ae6f8a73c336ed4fe05ace5de86d8991d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(arm): add extra hash config to validate ROTPK

The default mbedTLS configuration enables hash algorithms based on
the HASH_ALG or MBOOT_EL_HASH_ALG selected. However, the Arm ROTPK
is always embe

fix(arm): add extra hash config to validate ROTPK

The default mbedTLS configuration enables hash algorithms based on
the HASH_ALG or MBOOT_EL_HASH_ALG selected. However, the Arm ROTPK
is always embedded as a SHA256 hash in BL1 and BL2. In the future,
we may need to adjust this to use the HASH_ALG algorithm for
embedding the ROTPK hash.

As a temporary workaround, a separate mbedTLS configuration has
been created for Arm platforms to explicitly set SHA256 defines,
rather than relying on the default configuration. This adjustment
is reflected in the mbedTLS configuration file for the TC platform
as well as in the PSA Crypto configuration file.

Change-Id: Ib3128ce7b0fb5c0858624ecbc998d456968beddf
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(tc): make TCR2 feature asymmetric

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I6209dc46ddecaa09cc1220fe9488b3771ea6dc38

feat(rdv3): set CTX_INCLUDE_SVE_REGS build flag for RD-V3 variants

Commit 4242262(feat(simd):add sve state to simd ctxt struct)
introduced the CTX_INCLUDE_SVE_REGS build flag that needs to be set
if

feat(rdv3): set CTX_INCLUDE_SVE_REGS build flag for RD-V3 variants

Commit 4242262(feat(simd):add sve state to simd ctxt struct)
introduced the CTX_INCLUDE_SVE_REGS build flag that needs to be set
if SVE is enabled for more than one world, which is the case for
RD-V3. This build flag enables SVE registers to be included when
saving and restoring the CPU context.

Change-Id: Ic491939061e42e8c87a805ded99e271308f90352
Signed-off-by: Gautham Ravichandran <gautham.ravichandran@arm.com>

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Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME a

Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4

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feat(tc): enable SME and SME2 options for TC4

Set the Make flags for TF-A to be able to enable SME and SME2 features.
Note that we enable these architectural features for both the secure and
non-sec

feat(tc): enable SME and SME2 options for TC4

Set the Make flags for TF-A to be able to enable SME and SME2 features.
Note that we enable these architectural features for both the secure and
non-secure worlds, which is required on TC4.

In the case of the non-secure world, we specify a value of 2 for the
flag which specifies that TF-A should check the feature register to
ensure that the feature is present before enabling it. This allows these
flags to be compatible with all platforms and stops TF-A doing anything
different if it does not detect that the feature is present.

Change-Id: I51f8c7e3eb1cf06767f4b155c93269e1f129f730
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add system generic timer register definition for TC4

Add new include (specific to TC4) to the TC platform file which
specifies the system generic timer base address and is used by the TF-a

feat(tc): add system generic timer register definition for TC4

Add new include (specific to TC4) to the TC platform file which
specifies the system generic timer base address and is used by the TF-a
for use as system counters.

Note that this include must come before arm_def.h. This is required
as it checks if ARM_SYS_CNTCTL macros are defined before defining
its own macros.

Change-Id: I56861e5737271b29f09c75d962533be620766b52
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): allow TARGET_VERSION=4

Add basic support for TARGET_VERSION=4. It extends the existing 'if'
statements in the Makefile and the header to allow them to take the
value of 4 and also specifie

feat(tc): allow TARGET_VERSION=4

Add basic support for TARGET_VERSION=4. It extends the existing 'if'
statements in the Makefile and the header to allow them to take the
value of 4 and also specifies the SCMI platform info to use for TC4.

Change-Id: I8d8257671314277a133e88ef65fae8fada93d00e
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add MHUv3 register addresses for TC4

Change-Id: I06351fc048d792943f338291f8f64827339e8e1c
Signed-off-by: Leo Yan <leo.yan@arm.com>

fix(corstone-1000): fix Makefile error reporting

When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instea

fix(corstone-1000): fix Makefile error reporting

When trying to build for the Corstone-1000 platform without specifying a
valid TARGET_PLATFORM value, the "make" call reports a Makefile error
instead of the expected error messages pointing to the variable
omission:
====================
platform.mk: *** recipe commences before first target. Stop.
====================
This is due to the make's infamous special handling of the tab
character.

Fix the error report by replacing the tab with spaces.

Change-Id: I38264b6731793e5d5b929c189bb963e55bd5ce2d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure,

refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1

* Currently, EL1 context is included in cpu_context_t by default
for all the build configurations.
As part of the cpu context structure, we hold a copy of EL1, EL2
system registers, per world per PE. This context structure is
enormous and will continue to grow bigger with the addition of
new features incorporating new registers.

* Ideally, EL3 should save and restore the system registers at its next
lower exception level, which is EL2 in majority of the configurations.

* This patch aims at optimising the memory allocation in cases, when
the members from the context structure are unused. So el1 system
register context must be omitted when lower EL is always x-EL2.

* "CTX_INCLUDE_EL2_REGS" is the internal build flag which gets set,
when SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1.
It indicates, the system registers at EL2 are context switched for
the respective build configuration. Here, there is no need to save
and restore EL1 system registers, while x-EL2 is enabled.

Henceforth, this patch addresses this issue, by taking out the EL1
context at all possible places, while EL2 (CTX_INCLUDE_EL2_REGS) is
enabled, there by saving memory.

Change-Id: Ifddc497d3c810e22a15b1c227a731bcc133c2f4a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to wr

chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code

SCTLR_EL1 and TCR_EL1 regs are included either as part of errata
"ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure.
The code to write and read into these context entries, looks
repetitive and is invoked at most places.
This section is refactored to bring them under a static procedure,
keeping the code neat and easier to maintain.

Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): ad

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management

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feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are all

feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.

Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad7

feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad74bb9ee5c944
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778

feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778616e167ba6894195
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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