1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# By default dont build CPUs with no FVP model. 35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 36 37ENABLE_FEAT_AMU := 2 38ENABLE_FEAT_AMUv1p1 := 2 39ENABLE_FEAT_HCX := 2 40ENABLE_FEAT_RNG := 2 41ENABLE_FEAT_TWED := 2 42ENABLE_FEAT_GCS := 2 43 44ifeq (${ARCH}, aarch64) 45 46ifeq (${SPM_MM}, 0) 47ifeq (${CTX_INCLUDE_FPREGS}, 0) 48 ENABLE_SME_FOR_NS := 2 49 ENABLE_SME2_FOR_NS := 2 50else 51 ENABLE_SVE_FOR_NS := 0 52 ENABLE_SME_FOR_NS := 0 53 ENABLE_SME2_FOR_NS := 0 54endif 55endif 56 57 ENABLE_BRBE_FOR_NS := 2 58 ENABLE_TRBE_FOR_NS := 2 59endif 60 61ENABLE_SYS_REG_TRACE_FOR_NS := 2 62ENABLE_FEAT_CSV2_2 := 2 63ENABLE_FEAT_CSV2_3 := 2 64ENABLE_FEAT_DEBUGV8P9 := 2 65ENABLE_FEAT_DIT := 2 66ENABLE_FEAT_PAN := 2 67ENABLE_FEAT_VHE := 2 68CTX_INCLUDE_NEVE_REGS := 2 69ENABLE_FEAT_SEL2 := 2 70ENABLE_TRF_FOR_NS := 2 71ENABLE_FEAT_ECV := 2 72ENABLE_FEAT_FGT := 2 73ENABLE_FEAT_FGT2 := 2 74ENABLE_FEAT_THE := 2 75ENABLE_FEAT_TCR2 := 2 76ENABLE_FEAT_S2PIE := 2 77ENABLE_FEAT_S1PIE := 2 78ENABLE_FEAT_S2POE := 2 79ENABLE_FEAT_S1POE := 2 80ENABLE_FEAT_MTE2 := 2 81 82# The FVP platform depends on this macro to build with correct GIC driver. 83$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 84 85# Pass FVP_CLUSTER_COUNT to the build system. 86$(eval $(call add_define,FVP_CLUSTER_COUNT)) 87 88# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 89$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 90 91# Pass FVP_MAX_PE_PER_CPU to the build system. 92$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 93 94# Pass FVP_GICR_REGION_PROTECTION to the build system. 95$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 96 97# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 98$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 99 100# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 101# choose the CCI driver , else the CCN driver 102ifeq ($(FVP_CLUSTER_COUNT), 0) 103$(error "Incorrect cluster count specified for FVP port") 104else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 105FVP_INTERCONNECT_DRIVER := FVP_CCI 106else 107FVP_INTERCONNECT_DRIVER := FVP_CCN 108endif 109 110$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 111 112# Choose the GIC sources depending upon the how the FVP will be invoked 113ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 114 115# The GIC model (GIC-600 or GIC-500) will be detected at runtime 116GICV3_SUPPORT_GIC600 := 1 117GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 118 119# Include GICv3 driver files 120include drivers/arm/gic/v3/gicv3.mk 121 122FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 123 plat/common/plat_gicv3.c \ 124 plat/arm/common/arm_gicv3.c 125 126 ifeq ($(filter 1,${RESET_TO_BL2} \ 127 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 128 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 129 endif 130 131else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 132 133# No GICv4 extension 134GIC_ENABLE_V4_EXTN := 0 135$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 136 137# Include GICv2 driver files 138include drivers/arm/gic/v2/gicv2.mk 139 140FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 141 plat/common/plat_gicv2.c \ 142 plat/arm/common/arm_gicv2.c 143 144FVP_DT_PREFIX := fvp-base-gicv2-psci 145else 146$(error "Incorrect GIC driver chosen on FVP port") 147endif 148 149ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 150FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 151else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 152FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 153 plat/arm/common/arm_ccn.c 154else 155$(error "Incorrect CCN driver chosen on FVP port") 156endif 157 158FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 159 plat/arm/board/fvp/fvp_security.c \ 160 plat/arm/common/arm_tzc400.c 161 162 163PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 164 -Iinclude/lib/psa 165 166 167PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 168 169FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 170 171ifeq (${ARCH}, aarch64) 172 173# select a different set of CPU files, depending on whether we compile for 174# hardware assisted coherency cores or not 175ifeq (${HW_ASSISTED_COHERENCY}, 0) 176# Cores used without DSU 177 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 178 lib/cpus/aarch64/cortex_a53.S \ 179 lib/cpus/aarch64/cortex_a57.S \ 180 lib/cpus/aarch64/cortex_a72.S \ 181 lib/cpus/aarch64/cortex_a73.S 182else 183# Cores used with DSU only 184 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 185 # AArch64-only cores 186 # TODO: add all cores to the appropriate lists 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 188 lib/cpus/aarch64/cortex_a65ae.S \ 189 lib/cpus/aarch64/cortex_a76.S \ 190 lib/cpus/aarch64/cortex_a76ae.S \ 191 lib/cpus/aarch64/cortex_a77.S \ 192 lib/cpus/aarch64/cortex_a78.S \ 193 lib/cpus/aarch64/cortex_a78_ae.S \ 194 lib/cpus/aarch64/cortex_a78c.S \ 195 lib/cpus/aarch64/cortex_a710.S \ 196 lib/cpus/aarch64/cortex_a715.S \ 197 lib/cpus/aarch64/cortex_a720.S \ 198 lib/cpus/aarch64/neoverse_n_common.S \ 199 lib/cpus/aarch64/neoverse_n1.S \ 200 lib/cpus/aarch64/neoverse_n2.S \ 201 lib/cpus/aarch64/neoverse_v1.S \ 202 lib/cpus/aarch64/neoverse_e1.S \ 203 lib/cpus/aarch64/cortex_x2.S \ 204 lib/cpus/aarch64/cortex_x4.S 205 endif 206 # AArch64/AArch32 cores 207 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 208 lib/cpus/aarch64/cortex_a75.S 209endif 210 211#Build AArch64-only CPUs with no FVP model yet. 212ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 213 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 214 lib/cpus/aarch64/cortex_gelas.S \ 215 lib/cpus/aarch64/nevis.S \ 216 lib/cpus/aarch64/travis.S 217endif 218 219else 220FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 221 lib/cpus/aarch32/cortex_a57.S \ 222 lib/cpus/aarch32/cortex_a53.S 223endif 224 225BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 226 drivers/arm/sp805/sp805.c \ 227 drivers/delay_timer/delay_timer.c \ 228 drivers/io/io_semihosting.c \ 229 lib/semihosting/semihosting.c \ 230 lib/semihosting/${ARCH}/semihosting_call.S \ 231 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 232 plat/arm/board/fvp/fvp_bl1_setup.c \ 233 plat/arm/board/fvp/fvp_cpu_pwr.c \ 234 plat/arm/board/fvp/fvp_err.c \ 235 plat/arm/board/fvp/fvp_io_storage.c \ 236 plat/arm/board/fvp/fvp_topology.c \ 237 ${FVP_CPU_LIBS} \ 238 ${FVP_INTERCONNECT_SOURCES} 239 240ifeq (${USE_SP804_TIMER},1) 241BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 242else 243BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 244endif 245 246 247BL2_SOURCES += drivers/arm/sp805/sp805.c \ 248 drivers/io/io_semihosting.c \ 249 lib/utils/mem_region.c \ 250 lib/semihosting/semihosting.c \ 251 lib/semihosting/${ARCH}/semihosting_call.S \ 252 plat/arm/board/fvp/fvp_bl2_setup.c \ 253 plat/arm/board/fvp/fvp_err.c \ 254 plat/arm/board/fvp/fvp_io_storage.c \ 255 plat/arm/common/arm_nor_psci_mem_protect.c \ 256 ${FVP_SECURITY_SOURCES} 257 258 259ifeq (${COT_DESC_IN_DTB},1) 260BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 261endif 262 263ifeq (${ENABLE_RME},1) 264BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 265 plat/arm/board/fvp/fvp_cpu_pwr.c 266 267BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 268 plat/arm/board/fvp/fvp_realm_attest_key.c \ 269 plat/arm/board/fvp/fvp_el3_token_sign.c 270endif 271 272ifeq (${ENABLE_FEAT_RNG_TRAP},1) 273BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 274endif 275 276ifeq (${RESET_TO_BL2},1) 277BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 278 plat/arm/board/fvp/fvp_cpu_pwr.c \ 279 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 280 ${FVP_CPU_LIBS} \ 281 ${FVP_INTERCONNECT_SOURCES} 282endif 283 284ifeq (${USE_SP804_TIMER},1) 285BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 286endif 287 288BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 289 ${FVP_SECURITY_SOURCES} 290 291ifeq (${USE_SP804_TIMER},1) 292BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 293endif 294 295BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 296 drivers/arm/smmu/smmu_v3.c \ 297 drivers/delay_timer/delay_timer.c \ 298 drivers/cfi/v2m/v2m_flash.c \ 299 lib/utils/mem_region.c \ 300 plat/arm/board/fvp/fvp_bl31_setup.c \ 301 plat/arm/board/fvp/fvp_console.c \ 302 plat/arm/board/fvp/fvp_pm.c \ 303 plat/arm/board/fvp/fvp_topology.c \ 304 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 305 plat/arm/board/fvp/fvp_cpu_pwr.c \ 306 plat/arm/common/arm_nor_psci_mem_protect.c \ 307 ${FVP_CPU_LIBS} \ 308 ${FVP_GIC_SOURCES} \ 309 ${FVP_INTERCONNECT_SOURCES} \ 310 ${FVP_SECURITY_SOURCES} 311 312# Support for fconf in BL31 313# Added separately from the above list for better readability 314ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 315BL31_SOURCES += lib/fconf/fconf.c \ 316 lib/fconf/fconf_dyn_cfg_getter.c \ 317 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 318 319BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 320 321ifeq (${SEC_INT_DESC_IN_FCONF},1) 322BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 323endif 324 325endif 326 327ifeq (${USE_SP804_TIMER},1) 328BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 329else 330BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 331endif 332 333# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 334ifdef UNIX_MK 335FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 336FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 337 338FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 339$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 340 341ifeq (${TRANSFER_LIST}, 1) 342FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 343 ${PLAT}_tb_fw_config.dts \ 344 ) 345else 346FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 347 ${PLAT}_fw_config.dts \ 348 ${PLAT}_tb_fw_config.dts \ 349 ${PLAT}_soc_fw_config.dts \ 350 ${PLAT}_nt_fw_config.dts \ 351 ) 352 353FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 354FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 355FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 356 357ifeq (${SPD},tspd) 358FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 359FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 360 361# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 362$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 363endif 364 365ifeq (${SPD},spmd) 366 367ifeq ($(ARM_SPMC_MANIFEST_DTS),) 368ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 369endif 370 371FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 372FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 373 374# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 376endif 377 378# Add the FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 380# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 381$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 382# Add the NT_FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 384endif 385 386# Add the TB_FW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 388# Add the HW_CONFIG to FIP and specify the same to certtool 389$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 390endif 391 392ifeq (${TRANSFER_LIST}, 1) 393include lib/transfer_list/transfer_list.mk 394 395ifeq ($(RESET_TO_BL31), 1) 396HW_CONFIG := ${FVP_HW_CONFIG} 397FW_HANDOFF_SIZE := 20000 398 399TRANSFER_LIST_DTB_OFFSET := 0x20 400$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 401endif 402endif 403 404# Enable dynamic mitigation support by default 405DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 406 407ifneq (${ENABLE_FEAT_AMU},0) 408BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 409 lib/cpus/aarch64/cpuamu_helpers.S 410 411ifeq (${HW_ASSISTED_COHERENCY}, 1) 412BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 413 lib/cpus/aarch64/neoverse_n1_pubsub.c 414endif 415endif 416 417ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 418 ifeq (${ENABLE_FEAT_RAS},1) 419 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 420 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 421 else 422 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 423 endif 424 else 425 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 426 endif 427endif 428 429ifneq (${ENABLE_STACK_PROTECTOR},0) 430PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 431endif 432 433# Enable the dynamic translation tables library. 434ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 435 ifeq (${ARCH},aarch32) 436 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 437 else # AArch64 438 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 439 endif 440endif 441 442ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 443 ifeq (${ARCH},aarch32) 444 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 445 else # AArch64 446 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 447 ifeq (${SPD},tspd) 448 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 449 endif 450 endif 451endif 452 453ifeq (${USE_DEBUGFS},1) 454 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 455endif 456 457# Add support for platform supplied linker script for BL31 build 458$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 459 460ifneq (${RESET_TO_BL2}, 0) 461 override BL1_SOURCES = 462endif 463 464include plat/arm/board/common/board_common.mk 465include plat/arm/common/arm_common.mk 466 467ifeq (${MEASURED_BOOT},1) 468BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 469 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 470 lib/psa/measured_boot.c 471 472BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 473 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 474 lib/psa/measured_boot.c 475endif 476 477ifeq (${DRTM_SUPPORT}, 1) 478BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 479 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 480 plat/arm/board/fvp/fvp_drtm_err.c \ 481 plat/arm/board/fvp/fvp_drtm_measurement.c \ 482 plat/arm/board/fvp/fvp_drtm_stub.c \ 483 plat/arm/common/arm_dyn_cfg.c \ 484 plat/arm/board/fvp/fvp_err.c 485endif 486 487ifeq (${TRUSTED_BOARD_BOOT}, 1) 488BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 489BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 490 491# FVP being a development platform, enable capability to disable Authentication 492# dynamically if TRUSTED_BOARD_BOOT is set. 493DYN_DISABLE_AUTH := 1 494endif 495 496ifeq (${SPMC_AT_EL3}, 1) 497PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 498endif 499 500PSCI_OS_INIT_MODE := 1 501 502ifeq (${SPD},spmd) 503BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 504endif 505 506# Test specific macros, keep them at bottom of this file 507$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 508ifeq (${PLATFORM_TEST_EA_FFH}, 1) 509 ifeq (${FFH_SUPPORT}, 0) 510 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 511 endif 512 513endif 514 515$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 516ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 517 ifeq (${ENABLE_FEAT_RAS}, 0) 518 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 519 endif 520 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 521 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 522 endif 523endif 524 525$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 526ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 527 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 528 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 529 endif 530 ifeq (${ENABLE_SPMD_LP}, 0) 531 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 532 endif 533 ifeq (${ENABLE_FEAT_RAS}, 0) 534 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 535 endif 536 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 537 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 538 endif 539endif 540 541ifeq (${ERRATA_ABI_SUPPORT}, 1) 542include plat/arm/board/fvp/fvp_cpu_errata.mk 543endif 544 545# Build macro necessary for running SPM tests on FVP platform 546$(eval $(call add_define,PLAT_TEST_SPM)) 547