feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME rela

feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.

This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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Merge changes from topic "hold-pen-generic" into integration

* changes:
fix(corstone-1000): use generic hold pen
refactor(platforms): add generic hold pen

Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (n

fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (not cache-line aligned)
and only wrote GO to the target slot without touching other slots
or flushing to main memory. This is broken because:

1. Secondary CPUs write WAIT from non-cached context (MMU off in BL2)
2. The BL2-to-BL31 transition does dcsw_op_all (flush all caches)
3. This pushes stale cached data over the WAIT values in memory
4. The primary's GO write + DSB is insufficient -- it only ensures
ordering, not visibility to non-cached observers

plat_hold_pen_init() is called once at boot (from
plat_arm_psci_override_pm_ops) to write HOLD_STATE_WAIT into every
cache-line-aligned slot and flush the region. Then
plat_hold_pen_signal() writes just the target slot with the warm
boot entrypoint, flushes it, and issues SEV. Secondaries use the
plat_hold_pen_wait_and_jump macro to poll and branch directly to
the entrypoint stored in their hold slot.

Change-Id: I8fc533650c663700dab9bf47c0a79d9bb1236b17
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runt

Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runtime): use arm_gicr_base_addrs for sp-min

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feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic chec

feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic checks.

Change-Id: Ib52bbd8ce1850bbc7d5f72e6f29a208c3ba534d3
Signed-off-by: Alex Chapman <alex.chapman@arm.com>

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fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(l

fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(like RAS) in the standard platform hooks. To do that, the GIC needs to
be set up and ready to use before calling the platform hooks but
currently that is only done after. Annoyingly, a handful of platforms
need to set their GIC up before initialising it necessitating the
platform hooks to be called before GIC init.

This patch resolves this contradiction by moving the general GIC setup
calls to before the platform hooks and adding a GIC-specific platform
hook just before GIC per CPU init. This way both types of platforms can
do their business at the same time.

Change-Id: I361f587ab4603162ee880addb074800cbbb97b49
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore: bump eventlog library and interface changes

The eventlog library exposed macros TPM_ALG_SHA*. These will clash
with libTPM, so must be namespaced by prefixing them with EVLOG_

Change-Id: Id4

chore: bump eventlog library and interface changes

The eventlog library exposed macros TPM_ALG_SHA*. These will clash
with libTPM, so must be namespaced by prefixing them with EVLOG_

Change-Id: Id498d5882edda056c2d78c916193053655b3eb89
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>

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feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the

feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the FF-A v1.3 ALP2 specification.

The callback relies on helper utilities that enable the LSP to send
live activation framework messages to SPMC after performing several
sanity checks.

Change-Id: I2730433ec57c0c1163281eff9de729c6e93f3366
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being li

feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being live activated.
Necessary attributes of these two Secure Partitions are defined to
allow the LFA agent to report them to the host when the host performs
initial discovery of LFA support.

BREAKING CHANGE: Temporarily failing to build

Change-Id: Ibf0405559543cf19aaf45637c11ba5cf2e3a1619
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
pla

feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
placeholders.

Subsequent patches will implement the required functionality.

BREAKING CHANGE: Temporarily fails to build

Change-Id: Id733eaa0e7a300386b720fcce99ea265fd382ab6
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live acti

feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live activation of a physical SP.

BREAKING CHANGE: Temporarily fails to build

Change-Id: I1b7dcf91e08fc7d85b47f2b39330d1351f8294dd
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Tem

chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Temporary fails to build

Change-Id: I49a6941a18d2357092dcebf3e882a86e5ac8991f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(romlib): gate RSA jump table entries" into integration

fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf00812

fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf008126752faec2ab7986e4b1a566b717
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "refactor(platforms): remove A5DS platform (EOL)" into integration

Merge "fix(juno): debug build fail with MEASURED_BOOT and SPMC_AT_EL3" into integration

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STE

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic

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fix(juno): debug build fail with MEASURED_BOOT and SPMC_AT_EL3

There is debug build failure with MEASURED_BOOT and SPMC_AT_EL3
because of exceeding BL2 RAM size:

...
07:37:41 bin/ld: region `RA

fix(juno): debug build fail with MEASURED_BOOT and SPMC_AT_EL3

There is debug build failure with MEASURED_BOOT and SPMC_AT_EL3
because of exceeding BL2 RAM size:

...
07:37:41 bin/ld: region `RAM' overflowed by 4096 bytes
07:37:41 collect2: error: ld returned 1 exit status
...

To fix this, increase the BL2 RAM size when
MEASURED_BOOT and SPMC_AT_EL3 options are used.

Fixes: b50c7af1f59b ("Merge changes from topic "hm/evlog" into integration")
Change-Id: I8006ebeda51e4b905beecb1c5c7e6e907f6baef7
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(juno): increase BL2 stack size when MEASURED_BOOT

When MEASURED_BOOT is enabled, a stack overflow occurs
while generating the data hash for the event log
using the mbedtls library.

To address

feat(juno): increase BL2 stack size when MEASURED_BOOT

When MEASURED_BOOT is enabled, a stack overflow occurs
while generating the data hash for the event log
using the mbedtls library.

To address this issue, increase the BL2 stack size
when MEASURED_BOOT is enabled.

Change-Id: I36b9c0c714e409f66ae000c960ea1be5e0e749a9
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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