Merge "feat(fvp): define ns memory in the SPMC manifest" into integration

Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd

Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI
feat(spmd): register handler for group0 interrupt from NWd

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feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.

feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.
The NS memory that is not used by SPs will be assigned
to the NWd, for it to share memory with SPs as needed.
Thus, this limits the memory the NWd can share with SPs,
to prevent NWD VMs from sharing memory that belongs
to other critical components.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28

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Merge "fix(sme): disable SME for SPD=spmd" into integration

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder fo

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder for future Group0 interrupt sources.

Moreover, this patch also provides a dummy implementation of the
above mentioned platform hook for QEMU, corstone100, n1sdp and
hikey960 ports.

Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integration

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the

feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the scenarios sensibly we need a proper handling when the FVP is
under test so that we do not change the default behavior.

Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI
scripts and implement a proper handling for Sync EA and SErrors from
lower EL.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b

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Merge "feat(sme): enable SME2 functionality for NS world" into integration

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations ef

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.

This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.

Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.

Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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build(fvp): reduce the number of cpu libraries included by default

The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=

build(fvp): reduce the number of cpu libraries included by default

The fvp build includes a very large number of cpus so that it can run on
a wide range of models. One config (HW_ASSISTED_COHERENCY=1
CTX_INCLUDE_AARCH32_REGS=0) includes an unusually large number of cpus.
Well, the list is quite arbitrary and incomplete. As we're currently out
of BL31 space on the fvp, remove all that are not routinely run in the
CI to buy us some time.

Also use the opportunity to reorder the list into something searchable.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8c6cad41327451edf0d3a0e92c43d6c72c254aac

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refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED

At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED

At the moment we only support FEAT_DIT to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_DIT=2), by splitting
is_armv8_4_dit_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed).

We use ENABLE_DIT in two occassions in assembly code, where we just set
the DIT bit in the DIT system register.
Protect those two cases by reading the CPU ID register when ENABLE_DIT
is set to 2.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(gcs): support guarded control stack" into integration

fix(fvp): correct ehf priority for SPM_MM

PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure i

fix(fvp): correct ehf priority for SPM_MM

PLAT_SP_PRI is used by SPM_MM and it is assigned same value as RAS
priority. Which is not allowed by exception handling framework and
causes build failure if both SPM_MM and RAS is enabled.

To fix this problem assign SP a different priority than RAS.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iff64ac547f0966c0d94ac7c3ab0eb1e3151fb314

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feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size a

feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size allocated by BL1 is
passed to BL2, rather than both relying on the maximum Event Log buffer
size macro.

Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the c

feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the current call stack without requiring a full stack
unwind. Enable access to this feature for EL2 and below, context
switching the newly added EL2 registers as appropriate.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b

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feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the

feat(pie/por): support permission indirection and overlay

Arm v8.9 introduces a series of features providing a new way to set memory
permissions. Instead of directly encoding the permissions in the page
tables the PTEs contain indexes into an array of permissions stored in
system registers, allowing greater flexibility and density of encoding.

Enable access to these features for EL2 and below, context switching the
newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E
are separately discoverable we have separate build time options for
enabling them, but note that there is overlap in the registers that they
implement and the enable bit required for lower EL access.

Change the FVP platform to default to handling them as dynamic options so
the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Icf89e444e39e1af768739668b505661df18fb234

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Merge "fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded" into integration

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

Change-Id: I4750e774732218ee669dceb734cd107f46b78492
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

C

feat(cpus): add support for chaberton cpu

Add basic CPU library code to support the Chaberton CPU,
Chaberton cores are based out of Hunter core, so overall
library code was adapted based on that.

Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded

Just like the tspd, DRTM support pulls in a lot of code which can't fit
into SRAM with everything else the fvp is including. Luckily, testin

fix(fvp): work around DRTM_SUPPORT BL31 progbits exceeded

Just like the tspd, DRTM support pulls in a lot of code which can't fit
into SRAM with everything else the fvp is including. Luckily, testing
this feature is only done on v8.0 models, meaning all feature related
code can be excluded for this run, saving space. The benefit of doing it
this way is that the test can continue running unaltered in the interim.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iced2089837622fea49c10ae403c653dd1f331ca3

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fix(fvp): incorrect UUID name in FVP tb_fw_config

Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I557bca7dd32c3be084bbba11d84dfa281

fix(fvp): incorrect UUID name in FVP tb_fw_config

Signed-off-by: Rob Hughes <robert.hughes@arm.com>
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I557bca7dd32c3be084bbba11d84dfa2818cb6791

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fix(fvp): work around BL31 progbits exceeded

It is useful to have a single build for the FVP that includes as much
stuff as possible. Such a build allows a single TF-A build to be used on
a wide var

fix(fvp): work around BL31 progbits exceeded

It is useful to have a single build for the FVP that includes as much
stuff as possible. Such a build allows a single TF-A build to be used on
a wide variety of fvp command lines. Unfortunately, the fvp also has a
(somewhat arbitrary) SRAM limit and enabling a bunch of stuff overruns
what is available.

To workaround this limit, don't enable everything for all
configurations. The offending configuration is when tsp is enabled, so
try to slim the binary down only when building with it.

As this doesn't solve the issue of running out of space for BL31, update
the linker error to give some clue as to what has (likely) caused it
while more permanent fixes are found.

Also add FEAT_RNG to the mix as it got missed in the commotion.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Icb27cc837c2d90ca182693e9b3121b51383d51fd

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feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second fun

feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED

Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting
feat_sme_supported() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we do SME specific setup.

Change the FVP platform default to the now supported dynamic option
(=2),so the right decision can be made by the code at runtime.

Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEA

Merge changes from topic "psci-osi" into integration

* changes:
feat(sc7280): add support for PSCI_OS_INIT_MODE
feat(fvp): enable support for PSCI OS-initiated mode
feat(psci): update PSCI_FEATURES
feat(psci): add support for OS-initiated mode
feat(psci): add support for PSCI_SET_SUSPEND_MODE
build(psci): add build option for OS-initiated mode
docs(psci): add design proposal for OS-initiated mode

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