1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * APU specific definition of processors in the subsystem as well as functions 10 * for getting information about and changing state of the APU. 11 */ 12 13 #include <assert.h> 14 #include <plat_ipi.h> 15 #include <platform_def.h> 16 #include <versal_def.h> 17 #include <lib/bakery_lock.h> 18 #include <lib/mmio.h> 19 #include <lib/utils.h> 20 #include <drivers/arm/gicv3.h> 21 #include <drivers/arm/gic_common.h> 22 #include <plat/common/platform.h> 23 #include "pm_api_sys.h" 24 #include "pm_client.h" 25 #include "pm_defs.h" 26 27 #define UNDEFINED_CPUID (~0) 28 #define IRQ_MAX 142U 29 #define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U) 30 31 DEFINE_BAKERY_LOCK(pm_client_secure_lock); 32 33 static const struct pm_ipi apu_ipi = { 34 .local_ipi_id = IPI_ID_APU, 35 .remote_ipi_id = IPI_ID_PMC, 36 .buffer_base = IPI_BUFFER_APU_BASE, 37 }; 38 39 /* Order in pm_procs_all array must match cpu ids */ 40 static const struct pm_proc pm_procs_all[] = { 41 { 42 .node_id = XPM_DEVID_ACPU_0, 43 .ipi = &apu_ipi, 44 .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, 45 }, 46 { 47 .node_id = XPM_DEVID_ACPU_1, 48 .ipi = &apu_ipi, 49 .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, 50 } 51 }; 52 53 const struct pm_proc *primary_proc = &pm_procs_all[0]; 54 55 /* Interrupt to PM node index map */ 56 static enum pm_device_node_idx irq_node_map[IRQ_MAX + 1] = { 57 [13] = XPM_NODEIDX_DEV_GPIO, 58 [14] = XPM_NODEIDX_DEV_I2C_0, 59 [15] = XPM_NODEIDX_DEV_I2C_1, 60 [16] = XPM_NODEIDX_DEV_SPI_0, 61 [17] = XPM_NODEIDX_DEV_SPI_1, 62 [18] = XPM_NODEIDX_DEV_UART_0, 63 [19] = XPM_NODEIDX_DEV_UART_1, 64 [20] = XPM_NODEIDX_DEV_CAN_FD_0, 65 [21] = XPM_NODEIDX_DEV_CAN_FD_1, 66 [22] = XPM_NODEIDX_DEV_USB_0, 67 [23] = XPM_NODEIDX_DEV_USB_0, 68 [24] = XPM_NODEIDX_DEV_USB_0, 69 [25] = XPM_NODEIDX_DEV_USB_0, 70 [26] = XPM_NODEIDX_DEV_USB_0, 71 [37] = XPM_NODEIDX_DEV_TTC_0, 72 [38] = XPM_NODEIDX_DEV_TTC_0, 73 [39] = XPM_NODEIDX_DEV_TTC_0, 74 [40] = XPM_NODEIDX_DEV_TTC_1, 75 [41] = XPM_NODEIDX_DEV_TTC_1, 76 [42] = XPM_NODEIDX_DEV_TTC_1, 77 [43] = XPM_NODEIDX_DEV_TTC_2, 78 [44] = XPM_NODEIDX_DEV_TTC_2, 79 [45] = XPM_NODEIDX_DEV_TTC_2, 80 [46] = XPM_NODEIDX_DEV_TTC_3, 81 [47] = XPM_NODEIDX_DEV_TTC_3, 82 [48] = XPM_NODEIDX_DEV_TTC_3, 83 [56] = XPM_NODEIDX_DEV_GEM_0, 84 [57] = XPM_NODEIDX_DEV_GEM_0, 85 [58] = XPM_NODEIDX_DEV_GEM_1, 86 [59] = XPM_NODEIDX_DEV_GEM_1, 87 [60] = XPM_NODEIDX_DEV_ADMA_0, 88 [61] = XPM_NODEIDX_DEV_ADMA_1, 89 [62] = XPM_NODEIDX_DEV_ADMA_2, 90 [63] = XPM_NODEIDX_DEV_ADMA_3, 91 [64] = XPM_NODEIDX_DEV_ADMA_4, 92 [65] = XPM_NODEIDX_DEV_ADMA_5, 93 [66] = XPM_NODEIDX_DEV_ADMA_6, 94 [67] = XPM_NODEIDX_DEV_ADMA_7, 95 [74] = XPM_NODEIDX_DEV_USB_0, 96 [126] = XPM_NODEIDX_DEV_SDIO_0, 97 [127] = XPM_NODEIDX_DEV_SDIO_0, 98 [128] = XPM_NODEIDX_DEV_SDIO_1, 99 [129] = XPM_NODEIDX_DEV_SDIO_1, 100 [142] = XPM_NODEIDX_DEV_RTC, 101 }; 102 103 /** 104 * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number 105 * @irq: Interrupt number 106 * 107 * Return: PM node index corresponding to the specified interrupt 108 */ 109 static enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq) 110 { 111 assert(irq <= IRQ_MAX); 112 return irq_node_map[irq]; 113 } 114 115 /** 116 * pm_client_set_wakeup_sources - Set all devices with enabled interrupts as 117 * wake sources in the LibPM. 118 * @node_id: Node id of processor 119 */ 120 static void pm_client_set_wakeup_sources(uint32_t node_id) 121 { 122 uint32_t reg_num; 123 uint32_t device_id; 124 uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX] = { 0U }; 125 uintptr_t isenabler1 = PLAT_GICD_BASE_VALUE + GICD_ISENABLER + 4; 126 127 for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) { 128 uint32_t base_irq = reg_num << ISENABLER_SHIFT; 129 uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); 130 131 if (reg == 0U) { 132 continue; 133 } 134 135 while (reg != 0U) { 136 enum pm_device_node_idx node_idx; 137 uint32_t idx, irq, lowest_set = reg & (-reg); 138 enum pm_ret_status ret; 139 140 idx = __builtin_ctz(lowest_set); 141 irq = base_irq + idx; 142 143 if (irq > IRQ_MAX) { 144 break; 145 } 146 147 node_idx = irq_to_pm_node_idx(irq); 148 reg &= ~lowest_set; 149 150 if (node_idx > XPM_NODEIDX_DEV_MIN && node_idx < XPM_NODEIDX_DEV_MAX) { 151 if (pm_wakeup_nodes_set[node_idx] == 0U) { 152 /* Get device ID from node index */ 153 device_id = PERIPH_DEVID(node_idx); 154 ret = pm_set_wakeup_source(node_id, 155 device_id, 1, 156 SECURE_FLAG); 157 pm_wakeup_nodes_set[node_idx] = (ret == PM_RET_SUCCESS) ? 158 1 : 0; 159 } 160 } 161 } 162 } 163 } 164 165 /** 166 * pm_client_suspend() - Client-specific suspend actions 167 * 168 * This function should contain any PU-specific actions 169 * required prior to sending suspend request to PMU 170 * Actions taken depend on the state system is suspending to. 171 */ 172 void pm_client_suspend(const struct pm_proc *proc, uint32_t state) 173 { 174 bakery_lock_get(&pm_client_secure_lock); 175 176 if (state == PM_STATE_SUSPEND_TO_RAM) { 177 pm_client_set_wakeup_sources((uint32_t)proc->node_id); 178 } 179 180 /* Set powerdown request */ 181 mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) | 182 (uint32_t)proc->pwrdn_mask); 183 184 bakery_lock_release(&pm_client_secure_lock); 185 } 186 187 /** 188 * pm_client_abort_suspend() - Client-specific abort-suspend actions 189 * 190 * This function should contain any PU-specific actions 191 * required for aborting a prior suspend request 192 */ 193 void pm_client_abort_suspend(void) 194 { 195 /* Enable interrupts at processor level (for current cpu) */ 196 gicv3_cpuif_enable(plat_my_core_pos()); 197 198 bakery_lock_get(&pm_client_secure_lock); 199 200 /* Clear powerdown request */ 201 mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) & 202 ~((uint32_t)primary_proc->pwrdn_mask)); 203 204 bakery_lock_release(&pm_client_secure_lock); 205 } 206 207 /** 208 * pm_get_cpuid() - get the local cpu ID for a global node ID 209 * @nid: node id of the processor 210 * 211 * Return: the cpu ID (starting from 0) for the subsystem 212 */ 213 static uint32_t pm_get_cpuid(uint32_t nid) 214 { 215 for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) { 216 if (pm_procs_all[i].node_id == nid) { 217 return i; 218 } 219 } 220 return UNDEFINED_CPUID; 221 } 222 223 /** 224 * pm_client_wakeup() - Client-specific wakeup actions 225 * 226 * This function should contain any PU-specific actions 227 * required for waking up another APU core 228 */ 229 void pm_client_wakeup(const struct pm_proc *proc) 230 { 231 uint32_t cpuid = pm_get_cpuid(proc->node_id); 232 233 if (cpuid == UNDEFINED_CPUID) { 234 return; 235 } 236 237 bakery_lock_get(&pm_client_secure_lock); 238 239 /* clear powerdown bit for affected cpu */ 240 uint32_t val = mmio_read_32(FPD_APU_PWRCTL); 241 val &= ~(proc->pwrdn_mask); 242 mmio_write_32(FPD_APU_PWRCTL, val); 243 244 bakery_lock_release(&pm_client_secure_lock); 245 } 246 247 /** 248 * pm_get_proc() - returns pointer to the proc structure 249 * @cpuid: id of the cpu whose proc struct pointer should be returned 250 * 251 * Return: pointer to a proc structure if proc is found, otherwise NULL 252 */ 253 const struct pm_proc *pm_get_proc(uint32_t cpuid) 254 { 255 if (cpuid < ARRAY_SIZE(pm_procs_all)) { 256 return &pm_procs_all[cpuid]; 257 } 258 259 return NULL; 260 } 261