1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# TODO: make all of this unconditional (or only base the condition on 41# ARM_ARCH_* when the makefile supports it). 42ifneq (${SPD}, tspd) 43 ENABLE_FEAT_AMU := 2 44 ENABLE_FEAT_AMUv1p1 := 2 45 ENABLE_FEAT_HCX := 2 46 ENABLE_MPAM_FOR_LOWER_ELS := 2 47 ENABLE_FEAT_RNG := 2 48 ENABLE_FEAT_TWED := 2 49ifeq (${ARCH},aarch64) 50ifeq (${SPM_MM}, 0) 51ifeq (${ENABLE_RME}, 0) 52ifeq (${CTX_INCLUDE_FPREGS}, 0) 53 ENABLE_SME_FOR_NS := 2 54endif 55endif 56endif 57endif 58endif 59 60# enable unconditionally for all builds 61ifeq (${ARCH}, aarch64) 62ifeq (${ENABLE_RME},0) 63 ENABLE_BRBE_FOR_NS := 2 64endif 65endif 66ENABLE_TRBE_FOR_NS := 2 67ENABLE_SYS_REG_TRACE_FOR_NS := 2 68ENABLE_FEAT_CSV2_2 := 2 69ENABLE_FEAT_PAN := 2 70ENABLE_FEAT_VHE := 2 71CTX_INCLUDE_NEVE_REGS := 2 72ENABLE_FEAT_SEL2 := 2 73ENABLE_TRF_FOR_NS := 2 74ENABLE_FEAT_ECV := 2 75ENABLE_FEAT_FGT := 2 76ENABLE_FEAT_TCR2 := 2 77 78# The FVP platform depends on this macro to build with correct GIC driver. 79$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 80 81# Pass FVP_CLUSTER_COUNT to the build system. 82$(eval $(call add_define,FVP_CLUSTER_COUNT)) 83 84# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 85$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 86 87# Pass FVP_MAX_PE_PER_CPU to the build system. 88$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 89 90# Pass FVP_GICR_REGION_PROTECTION to the build system. 91$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 92 93# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 94# choose the CCI driver , else the CCN driver 95ifeq ($(FVP_CLUSTER_COUNT), 0) 96$(error "Incorrect cluster count specified for FVP port") 97else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 98FVP_INTERCONNECT_DRIVER := FVP_CCI 99else 100FVP_INTERCONNECT_DRIVER := FVP_CCN 101endif 102 103$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 104 105# Choose the GIC sources depending upon the how the FVP will be invoked 106ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 107 108# The GIC model (GIC-600 or GIC-500) will be detected at runtime 109GICV3_SUPPORT_GIC600 := 1 110GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 111 112# Include GICv3 driver files 113include drivers/arm/gic/v3/gicv3.mk 114 115FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 116 plat/common/plat_gicv3.c \ 117 plat/arm/common/arm_gicv3.c 118 119 ifeq ($(filter 1,${RESET_TO_BL2} \ 120 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 121 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 122 endif 123 124else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 125 126# No GICv4 extension 127GIC_ENABLE_V4_EXTN := 0 128$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 129 130# Include GICv2 driver files 131include drivers/arm/gic/v2/gicv2.mk 132 133FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 134 plat/common/plat_gicv2.c \ 135 plat/arm/common/arm_gicv2.c 136 137FVP_DT_PREFIX := fvp-base-gicv2-psci 138else 139$(error "Incorrect GIC driver chosen on FVP port") 140endif 141 142ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 143FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 144else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 145FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 146 plat/arm/common/arm_ccn.c 147else 148$(error "Incorrect CCN driver chosen on FVP port") 149endif 150 151FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 152 plat/arm/board/fvp/fvp_security.c \ 153 plat/arm/common/arm_tzc400.c 154 155 156PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 157 -Iinclude/lib/psa 158 159 160PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 161 162FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 163 164ifeq (${ARCH}, aarch64) 165 166# select a different set of CPU files, depending on whether we compile for 167# hardware assisted coherency cores or not 168ifeq (${HW_ASSISTED_COHERENCY}, 0) 169# Cores used without DSU 170 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 171 lib/cpus/aarch64/cortex_a53.S \ 172 lib/cpus/aarch64/cortex_a57.S \ 173 lib/cpus/aarch64/cortex_a72.S \ 174 lib/cpus/aarch64/cortex_a73.S 175else 176# Cores used with DSU only 177 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 178 # AArch64-only cores 179 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 180 lib/cpus/aarch64/cortex_a76ae.S \ 181 lib/cpus/aarch64/cortex_a77.S \ 182 lib/cpus/aarch64/cortex_a78.S \ 183 lib/cpus/aarch64/neoverse_n_common.S \ 184 lib/cpus/aarch64/neoverse_n1.S \ 185 lib/cpus/aarch64/neoverse_n2.S \ 186 lib/cpus/aarch64/neoverse_e1.S \ 187 lib/cpus/aarch64/neoverse_v1.S \ 188 lib/cpus/aarch64/neoverse_v2.S \ 189 lib/cpus/aarch64/cortex_a78_ae.S \ 190 lib/cpus/aarch64/cortex_a510.S \ 191 lib/cpus/aarch64/cortex_a710.S \ 192 lib/cpus/aarch64/cortex_a715.S \ 193 lib/cpus/aarch64/cortex_x3.S \ 194 lib/cpus/aarch64/cortex_a65.S \ 195 lib/cpus/aarch64/cortex_a65ae.S \ 196 lib/cpus/aarch64/cortex_a78c.S \ 197 lib/cpus/aarch64/cortex_hayes.S \ 198 lib/cpus/aarch64/cortex_hunter.S \ 199 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 200 lib/cpus/aarch64/cortex_x2.S \ 201 lib/cpus/aarch64/neoverse_poseidon.S \ 202 lib/cpus/aarch64/cortex_chaberton.S \ 203 lib/cpus/aarch64/cortex_blackhawk.S 204 endif 205 # AArch64/AArch32 cores 206 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 207 lib/cpus/aarch64/cortex_a75.S 208endif 209 210else 211FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 212 lib/cpus/aarch32/cortex_a57.S 213endif 214 215BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 216 drivers/arm/sp805/sp805.c \ 217 drivers/delay_timer/delay_timer.c \ 218 drivers/io/io_semihosting.c \ 219 lib/semihosting/semihosting.c \ 220 lib/semihosting/${ARCH}/semihosting_call.S \ 221 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 222 plat/arm/board/fvp/fvp_bl1_setup.c \ 223 plat/arm/board/fvp/fvp_err.c \ 224 plat/arm/board/fvp/fvp_io_storage.c \ 225 ${FVP_CPU_LIBS} \ 226 ${FVP_INTERCONNECT_SOURCES} 227 228ifeq (${USE_SP804_TIMER},1) 229BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 230else 231BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 232endif 233 234 235BL2_SOURCES += drivers/arm/sp805/sp805.c \ 236 drivers/io/io_semihosting.c \ 237 lib/utils/mem_region.c \ 238 lib/semihosting/semihosting.c \ 239 lib/semihosting/${ARCH}/semihosting_call.S \ 240 plat/arm/board/fvp/fvp_bl2_setup.c \ 241 plat/arm/board/fvp/fvp_err.c \ 242 plat/arm/board/fvp/fvp_io_storage.c \ 243 plat/arm/common/arm_nor_psci_mem_protect.c \ 244 ${FVP_SECURITY_SOURCES} 245 246 247ifeq (${COT_DESC_IN_DTB},1) 248BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 249endif 250 251ifeq (${ENABLE_RME},1) 252BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 253 254BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 255 plat/arm/board/fvp/fvp_realm_attest_key.c 256 257# FVP platform does not support RSS, but it can leverage RSS APIs to 258# provide hardcoded token/key on request. 259BL31_SOURCES += lib/psa/delegated_attestation.c 260 261endif 262 263ifeq (${ENABLE_FEAT_RNG_TRAP},1) 264BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 265endif 266 267ifeq (${RESET_TO_BL2},1) 268BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 269 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 270 ${FVP_CPU_LIBS} \ 271 ${FVP_INTERCONNECT_SOURCES} 272endif 273 274ifeq (${USE_SP804_TIMER},1) 275BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 276endif 277 278BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 279 ${FVP_SECURITY_SOURCES} 280 281ifeq (${USE_SP804_TIMER},1) 282BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 283endif 284 285BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 286 drivers/arm/smmu/smmu_v3.c \ 287 drivers/delay_timer/delay_timer.c \ 288 drivers/cfi/v2m/v2m_flash.c \ 289 lib/utils/mem_region.c \ 290 plat/arm/board/fvp/fvp_bl31_setup.c \ 291 plat/arm/board/fvp/fvp_console.c \ 292 plat/arm/board/fvp/fvp_pm.c \ 293 plat/arm/board/fvp/fvp_topology.c \ 294 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 295 plat/arm/common/arm_nor_psci_mem_protect.c \ 296 ${FVP_CPU_LIBS} \ 297 ${FVP_GIC_SOURCES} \ 298 ${FVP_INTERCONNECT_SOURCES} \ 299 ${FVP_SECURITY_SOURCES} 300 301# Support for fconf in BL31 302# Added separately from the above list for better readability 303ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 304BL31_SOURCES += lib/fconf/fconf.c \ 305 lib/fconf/fconf_dyn_cfg_getter.c \ 306 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 307 308BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 309 310ifeq (${SEC_INT_DESC_IN_FCONF},1) 311BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 312endif 313 314endif 315 316ifeq (${USE_SP804_TIMER},1) 317BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 318else 319BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 320endif 321 322# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 323ifdef UNIX_MK 324FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 325FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 326 ${PLAT}_fw_config.dts \ 327 ${PLAT}_tb_fw_config.dts \ 328 ${PLAT}_soc_fw_config.dts \ 329 ${PLAT}_nt_fw_config.dts \ 330 ) 331 332FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 333FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 334FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 335FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 336 337ifeq (${SPD},tspd) 338FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 339FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 340 341# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 342$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 343endif 344 345ifeq (${SPD},spmd) 346 347ifeq ($(ARM_SPMC_MANIFEST_DTS),) 348ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 349endif 350 351FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 352FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 353 354# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 355$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 356endif 357 358# Add the FW_CONFIG to FIP and specify the same to certtool 359$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 360# Add the TB_FW_CONFIG to FIP and specify the same to certtool 361$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 362# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 363$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 364# Add the NT_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 366 367FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 368$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 369 370# Add the HW_CONFIG to FIP and specify the same to certtool 371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 372endif 373 374# Enable dynamic mitigation support by default 375DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 376 377ifneq (${ENABLE_FEAT_AMU},0) 378BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 379 lib/cpus/aarch64/cpuamu_helpers.S 380 381ifeq (${HW_ASSISTED_COHERENCY}, 1) 382BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 383 lib/cpus/aarch64/neoverse_n1_pubsub.c 384endif 385endif 386 387ifeq (${RAS_EXTENSION},1) 388BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 389endif 390 391ifneq (${ENABLE_STACK_PROTECTOR},0) 392PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 393endif 394 395ifeq (${ARCH},aarch32) 396 NEED_BL32 := yes 397endif 398 399# Enable the dynamic translation tables library. 400ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 401 ifeq (${ARCH},aarch32) 402 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 403 else # AArch64 404 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 405 endif 406endif 407 408ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 409 ifeq (${ARCH},aarch32) 410 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 411 else # AArch64 412 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 413 ifeq (${SPD},tspd) 414 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 415 endif 416 endif 417endif 418 419ifeq (${USE_DEBUGFS},1) 420 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 421endif 422 423# Add support for platform supplied linker script for BL31 build 424$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 425 426ifneq (${RESET_TO_BL2}, 0) 427 override BL1_SOURCES = 428endif 429 430# RSS is not supported on FVP right now. Thus, we use the mocked version 431# of the provided PSA APIs. They return with success and hard-coded token/key. 432PLAT_RSS_NOT_SUPPORTED := 1 433 434# Include Measured Boot makefile before any Crypto library makefile. 435# Crypto library makefile may need default definitions of Measured Boot build 436# flags present in Measured Boot makefile. 437ifeq (${MEASURED_BOOT},1) 438 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 439 $(info Including ${RSS_MEASURED_BOOT_MK}) 440 include ${RSS_MEASURED_BOOT_MK} 441 442 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 443 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 444 endif 445 446 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 447 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 448endif 449 450include plat/arm/board/common/board_common.mk 451include plat/arm/common/arm_common.mk 452 453ifeq (${MEASURED_BOOT},1) 454BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 455 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 456 lib/psa/measured_boot.c 457 458BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 459 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 460 lib/psa/measured_boot.c 461 462# Even though RSS is not supported on FVP (see above), we support overriding 463# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 464# the code to detect any build regressions. The resulting firmware will not be 465# functional. 466ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 467 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 468 include drivers/arm/rss/rss_comms.mk 469 BL1_SOURCES += ${RSS_COMMS_SOURCES} 470 BL2_SOURCES += ${RSS_COMMS_SOURCES} 471 BL31_SOURCES += ${RSS_COMMS_SOURCES} 472 473 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 474 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 475 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 476endif 477 478endif 479 480ifeq (${DRTM_SUPPORT}, 1) 481BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 482 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 483 plat/arm/board/fvp/fvp_drtm_err.c \ 484 plat/arm/board/fvp/fvp_drtm_measurement.c \ 485 plat/arm/board/fvp/fvp_drtm_stub.c \ 486 plat/arm/common/arm_dyn_cfg.c \ 487 plat/arm/board/fvp/fvp_err.c 488endif 489 490ifeq (${TRUSTED_BOARD_BOOT}, 1) 491BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 492BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 493 494# FVP being a development platform, enable capability to disable Authentication 495# dynamically if TRUSTED_BOARD_BOOT is set. 496DYN_DISABLE_AUTH := 1 497endif 498 499ifeq (${SPMC_AT_EL3}, 1) 500PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 501endif 502 503PSCI_OS_INIT_MODE := 1 504