1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 if (is_feat_csv2_2_supported()) { 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 } 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 if (is_feat_csv2_2_supported()) { 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 } 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 #endif /* CTX_INCLUDE_EL2_REGS */ 278 } 279 280 /******************************************************************************* 281 * The following function performs initialization of the cpu_context 'ctx' 282 * for first use that is common to all security states, and sets the 283 * initial entrypoint state as specified by the entry_point_info structure. 284 * 285 * The EE and ST attributes are used to configure the endianness and secure 286 * timer availability for the new execution context. 287 ******************************************************************************/ 288 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 289 { 290 u_register_t scr_el3; 291 el3_state_t *state; 292 gp_regs_t *gp_regs; 293 294 /* Clear any residual register values from the context */ 295 zeromem(ctx, sizeof(*ctx)); 296 297 /* 298 * SCR_EL3 was initialised during reset sequence in macro 299 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 300 * affect the next EL. 301 * 302 * The following fields are initially set to zero and then updated to 303 * the required value depending on the state of the SPSR_EL3 and the 304 * Security state and entrypoint attributes of the next EL. 305 */ 306 scr_el3 = read_scr(); 307 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 308 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 309 310 /* 311 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 312 * Exception level as specified by SPSR. 313 */ 314 if (GET_RW(ep->spsr) == MODE_RW_64) { 315 scr_el3 |= SCR_RW_BIT; 316 } 317 318 /* 319 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 320 * Secure timer registers to EL3, from AArch64 state only, if specified 321 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 322 * bit always behaves as 1 (i.e. secure physical timer register access 323 * is not trapped) 324 */ 325 if (EP_GET_ST(ep->h.attr) != 0U) { 326 scr_el3 |= SCR_ST_BIT; 327 } 328 329 /* 330 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 331 * SCR_EL3.HXEn. 332 */ 333 if (is_feat_hcx_supported()) { 334 scr_el3 |= SCR_HXEn_BIT; 335 } 336 337 /* 338 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 339 * registers are trapped to EL3. 340 */ 341 #if ENABLE_FEAT_RNG_TRAP 342 scr_el3 |= SCR_TRNDR_BIT; 343 #endif 344 345 #if FAULT_INJECTION_SUPPORT 346 /* Enable fault injection from lower ELs */ 347 scr_el3 |= SCR_FIEN_BIT; 348 #endif 349 350 /* 351 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 352 */ 353 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 354 scr_el3 |= SCR_TCR2EN_BIT; 355 } 356 357 /* 358 * SCR_EL3.PIEN: Enable permission indirection and overlay 359 * registers for AArch64 if present. 360 */ 361 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 362 scr_el3 |= SCR_PIEN_BIT; 363 } 364 365 /* 366 * CPTR_EL3 was initialized out of reset, copy that value to the 367 * context register. 368 */ 369 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 370 371 /* 372 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 373 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 374 * next mode is Hyp. 375 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 376 * same conditions as HVC instructions and when the processor supports 377 * ARMv8.6-FGT. 378 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 379 * CNTPOFF_EL2 register under the same conditions as HVC instructions 380 * and when the processor supports ECV. 381 */ 382 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 383 || ((GET_RW(ep->spsr) != MODE_RW_64) 384 && (GET_M32(ep->spsr) == MODE32_hyp))) { 385 scr_el3 |= SCR_HCE_BIT; 386 387 if (is_feat_fgt_supported()) { 388 scr_el3 |= SCR_FGTEN_BIT; 389 } 390 391 if (is_feat_ecv_supported()) { 392 scr_el3 |= SCR_ECVEN_BIT; 393 } 394 } 395 396 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 397 if (is_feat_twed_supported()) { 398 /* Set delay in SCR_EL3 */ 399 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 400 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 401 << SCR_TWEDEL_SHIFT); 402 403 /* Enable WFE delay */ 404 scr_el3 |= SCR_TWEDEn_BIT; 405 } 406 407 /* 408 * Populate EL3 state so that we've the right context 409 * before doing ERET 410 */ 411 state = get_el3state_ctx(ctx); 412 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 413 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 414 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 415 416 /* 417 * Store the X0-X7 value from the entrypoint into the context 418 * Use memcpy as we are in control of the layout of the structures 419 */ 420 gp_regs = get_gpregs_ctx(ctx); 421 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 422 } 423 424 /******************************************************************************* 425 * Context management library initialization routine. This library is used by 426 * runtime services to share pointers to 'cpu_context' structures for secure 427 * non-secure and realm states. Management of the structures and their associated 428 * memory is not done by the context management library e.g. the PSCI service 429 * manages the cpu context used for entry from and exit to the non-secure state. 430 * The Secure payload dispatcher service manages the context(s) corresponding to 431 * the secure state. It also uses this library to get access to the non-secure 432 * state cpu context pointers. 433 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 434 * which will be used for programming an entry into a lower EL. The same context 435 * will be used to save state upon exception entry from that EL. 436 ******************************************************************************/ 437 void __init cm_init(void) 438 { 439 /* 440 * The context management library has only global data to intialize, but 441 * that will be done when the BSS is zeroed out. 442 */ 443 } 444 445 /******************************************************************************* 446 * This is the high-level function used to initialize the cpu_context 'ctx' for 447 * first use. It performs initializations that are common to all security states 448 * and initializations specific to the security state specified in 'ep' 449 ******************************************************************************/ 450 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 451 { 452 unsigned int security_state; 453 454 assert(ctx != NULL); 455 456 /* 457 * Perform initializations that are common 458 * to all security states 459 */ 460 setup_context_common(ctx, ep); 461 462 security_state = GET_SECURITY_STATE(ep->h.attr); 463 464 /* Perform security state specific initializations */ 465 switch (security_state) { 466 case SECURE: 467 setup_secure_context(ctx, ep); 468 break; 469 #if ENABLE_RME 470 case REALM: 471 setup_realm_context(ctx, ep); 472 break; 473 #endif 474 case NON_SECURE: 475 setup_ns_context(ctx, ep); 476 break; 477 default: 478 ERROR("Invalid security state\n"); 479 panic(); 480 break; 481 } 482 } 483 484 /******************************************************************************* 485 * Enable architecture extensions on first entry to Non-secure world. 486 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 487 * it is zero. 488 ******************************************************************************/ 489 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 490 { 491 #if IMAGE_BL31 492 if (is_feat_spe_supported()) { 493 spe_enable(el2_unused); 494 } 495 496 if (is_feat_amu_supported()) { 497 amu_enable(el2_unused, ctx); 498 } 499 500 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 501 if (is_feat_sme_supported()) { 502 sme_enable(ctx); 503 } else if (is_feat_sve_supported()) { 504 /* Enable SVE and FPU/SIMD for non-secure world. */ 505 sve_enable(ctx); 506 } 507 508 if (is_feat_mpam_supported()) { 509 mpam_enable(el2_unused); 510 } 511 512 if (is_feat_trbe_supported()) { 513 trbe_enable(); 514 } 515 516 if (is_feat_brbe_supported()) { 517 brbe_enable(); 518 } 519 520 if (is_feat_sys_reg_trace_supported()) { 521 sys_reg_trace_enable(ctx); 522 } 523 524 if (is_feat_trf_supported()) { 525 trf_enable(); 526 } 527 #endif 528 } 529 530 /******************************************************************************* 531 * Enable architecture extensions on first entry to Secure world. 532 ******************************************************************************/ 533 static void manage_extensions_secure(cpu_context_t *ctx) 534 { 535 #if IMAGE_BL31 536 537 if (is_feat_sme_supported()) { 538 if (ENABLE_SME_FOR_SWD) { 539 /* 540 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 541 * must ensure SME, SVE, and FPU/SIMD context properly managed. 542 */ 543 sme_enable(ctx); 544 } else { 545 /* 546 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 547 * world can safely use the associated registers. 548 */ 549 sme_disable(ctx); 550 } 551 } else if (is_feat_sve_supported()) { 552 if (ENABLE_SVE_FOR_SWD) { 553 /* 554 * Enable SVE and FPU in secure context, secure manager must 555 * ensure that the SVE and FPU register contexts are properly 556 * managed. 557 */ 558 sve_enable(ctx); 559 } else { 560 /* 561 * Disable SVE and FPU in secure context so non-secure world 562 * can safely use them. 563 */ 564 sve_disable(ctx); 565 } 566 } 567 568 #endif /* IMAGE_BL31 */ 569 } 570 571 /******************************************************************************* 572 * The following function initializes the cpu_context for a CPU specified by 573 * its `cpu_idx` for first use, and sets the initial entrypoint state as 574 * specified by the entry_point_info structure. 575 ******************************************************************************/ 576 void cm_init_context_by_index(unsigned int cpu_idx, 577 const entry_point_info_t *ep) 578 { 579 cpu_context_t *ctx; 580 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 581 cm_setup_context(ctx, ep); 582 } 583 584 /******************************************************************************* 585 * The following function initializes the cpu_context for the current CPU 586 * for first use, and sets the initial entrypoint state as specified by the 587 * entry_point_info structure. 588 ******************************************************************************/ 589 void cm_init_my_context(const entry_point_info_t *ep) 590 { 591 cpu_context_t *ctx; 592 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 593 cm_setup_context(ctx, ep); 594 } 595 596 /******************************************************************************* 597 * Prepare the CPU system registers for first entry into realm, secure, or 598 * normal world. 599 * 600 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 601 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 602 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 603 * For all entries, the EL1 registers are initialized from the cpu_context 604 ******************************************************************************/ 605 void cm_prepare_el3_exit(uint32_t security_state) 606 { 607 u_register_t sctlr_elx, scr_el3, mdcr_el2; 608 cpu_context_t *ctx = cm_get_context(security_state); 609 bool el2_unused = false; 610 uint64_t hcr_el2 = 0U; 611 612 assert(ctx != NULL); 613 614 if (security_state == NON_SECURE) { 615 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 616 CTX_SCR_EL3); 617 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 618 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 619 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 620 CTX_SCTLR_EL1); 621 sctlr_elx &= SCTLR_EE_BIT; 622 sctlr_elx |= SCTLR_EL2_RES1; 623 #if ERRATA_A75_764081 624 /* 625 * If workaround of errata 764081 for Cortex-A75 is used 626 * then set SCTLR_EL2.IESB to enable Implicit Error 627 * Synchronization Barrier. 628 */ 629 sctlr_elx |= SCTLR_IESB_BIT; 630 #endif 631 write_sctlr_el2(sctlr_elx); 632 } else if (el_implemented(2) != EL_IMPL_NONE) { 633 el2_unused = true; 634 635 /* 636 * EL2 present but unused, need to disable safely. 637 * SCTLR_EL2 can be ignored in this case. 638 * 639 * Set EL2 register width appropriately: Set HCR_EL2 640 * field to match SCR_EL3.RW. 641 */ 642 if ((scr_el3 & SCR_RW_BIT) != 0U) 643 hcr_el2 |= HCR_RW_BIT; 644 645 /* 646 * For Armv8.3 pointer authentication feature, disable 647 * traps to EL2 when accessing key registers or using 648 * pointer authentication instructions from lower ELs. 649 */ 650 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 651 652 write_hcr_el2(hcr_el2); 653 654 /* 655 * Initialise CPTR_EL2 setting all fields rather than 656 * relying on the hw. All fields have architecturally 657 * UNKNOWN reset values. 658 * 659 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 660 * accesses to the CPACR_EL1 or CPACR from both 661 * Execution states do not trap to EL2. 662 * 663 * CPTR_EL2.TTA: Set to zero so that Non-secure System 664 * register accesses to the trace registers from both 665 * Execution states do not trap to EL2. 666 * If PE trace unit System registers are not implemented 667 * then this bit is reserved, and must be set to zero. 668 * 669 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 670 * to SIMD and floating-point functionality from both 671 * Execution states do not trap to EL2. 672 */ 673 write_cptr_el2(CPTR_EL2_RESET_VAL & 674 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 675 | CPTR_EL2_TFP_BIT)); 676 677 /* 678 * Initialise CNTHCTL_EL2. All fields are 679 * architecturally UNKNOWN on reset and are set to zero 680 * except for field(s) listed below. 681 * 682 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 683 * Hyp mode of Non-secure EL0 and EL1 accesses to the 684 * physical timer registers. 685 * 686 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 687 * Hyp mode of Non-secure EL0 and EL1 accesses to the 688 * physical counter registers. 689 */ 690 write_cnthctl_el2(CNTHCTL_RESET_VAL | 691 EL1PCEN_BIT | EL1PCTEN_BIT); 692 693 /* 694 * Initialise CNTVOFF_EL2 to zero as it resets to an 695 * architecturally UNKNOWN value. 696 */ 697 write_cntvoff_el2(0); 698 699 /* 700 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 701 * MPIDR_EL1 respectively. 702 */ 703 write_vpidr_el2(read_midr_el1()); 704 write_vmpidr_el2(read_mpidr_el1()); 705 706 /* 707 * Initialise VTTBR_EL2. All fields are architecturally 708 * UNKNOWN on reset. 709 * 710 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 711 * 2 address translation is disabled, cache maintenance 712 * operations depend on the VMID. 713 * 714 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 715 * translation is disabled. 716 */ 717 write_vttbr_el2(VTTBR_RESET_VAL & 718 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 719 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 720 721 /* 722 * Initialise MDCR_EL2, setting all fields rather than 723 * relying on hw. Some fields are architecturally 724 * UNKNOWN on reset. 725 * 726 * MDCR_EL2.HLP: Set to one so that event counter 727 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 728 * occurs on the increment that changes 729 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 730 * implemented. This bit is RES0 in versions of the 731 * architecture earlier than ARMv8.5, setting it to 1 732 * doesn't have any effect on them. 733 * 734 * MDCR_EL2.TTRF: Set to zero so that access to Trace 735 * Filter Control register TRFCR_EL1 at EL1 is not 736 * trapped to EL2. This bit is RES0 in versions of 737 * the architecture earlier than ARMv8.4. 738 * 739 * MDCR_EL2.HPMD: Set to one so that event counting is 740 * prohibited at EL2. This bit is RES0 in versions of 741 * the architecture earlier than ARMv8.1, setting it 742 * to 1 doesn't have any effect on them. 743 * 744 * MDCR_EL2.TPMS: Set to zero so that accesses to 745 * Statistical Profiling control registers from EL1 746 * do not trap to EL2. This bit is RES0 when SPE is 747 * not implemented. 748 * 749 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 750 * EL1 System register accesses to the Debug ROM 751 * registers are not trapped to EL2. 752 * 753 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 754 * System register accesses to the powerdown debug 755 * registers are not trapped to EL2. 756 * 757 * MDCR_EL2.TDA: Set to zero so that System register 758 * accesses to the debug registers do not trap to EL2. 759 * 760 * MDCR_EL2.TDE: Set to zero so that debug exceptions 761 * are not routed to EL2. 762 * 763 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 764 * Monitors. 765 * 766 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 767 * EL1 accesses to all Performance Monitors registers 768 * are not trapped to EL2. 769 * 770 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 771 * and EL1 accesses to the PMCR_EL0 or PMCR are not 772 * trapped to EL2. 773 * 774 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 775 * architecturally-defined reset value. 776 * 777 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 778 * owning exception level is NS-EL1 and, tracing is 779 * prohibited at NS-EL2. These bits are RES0 when 780 * FEAT_TRBE is not implemented. 781 */ 782 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 783 MDCR_EL2_HPMD) | 784 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 785 >> PMCR_EL0_N_SHIFT)) & 786 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 787 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 788 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 789 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 790 MDCR_EL2_TPMCR_BIT | 791 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 792 793 write_mdcr_el2(mdcr_el2); 794 795 /* 796 * Initialise HSTR_EL2. All fields are architecturally 797 * UNKNOWN on reset. 798 * 799 * HSTR_EL2.T<n>: Set all these fields to zero so that 800 * Non-secure EL0 or EL1 accesses to System registers 801 * do not trap to EL2. 802 */ 803 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 804 /* 805 * Initialise CNTHP_CTL_EL2. All fields are 806 * architecturally UNKNOWN on reset. 807 * 808 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 809 * physical timer and prevent timer interrupts. 810 */ 811 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 812 ~(CNTHP_CTL_ENABLE_BIT)); 813 } 814 manage_extensions_nonsecure(el2_unused, ctx); 815 } 816 817 cm_el1_sysregs_context_restore(security_state); 818 cm_set_next_eret_context(security_state); 819 } 820 821 #if CTX_INCLUDE_EL2_REGS 822 823 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 824 { 825 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 826 if (is_feat_amu_supported()) { 827 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 828 } 829 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 830 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 831 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 832 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 833 } 834 835 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 836 { 837 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 838 if (is_feat_amu_supported()) { 839 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 840 } 841 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 842 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 843 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 844 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 845 } 846 847 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 848 { 849 u_register_t mpam_idr = read_mpamidr_el1(); 850 851 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 852 853 /* 854 * The context registers that we intend to save would be part of the 855 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 856 */ 857 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 858 return; 859 } 860 861 /* 862 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 863 * MPAMIDR_HAS_HCR_BIT == 1. 864 */ 865 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 866 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 867 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 868 869 /* 870 * The number of MPAMVPM registers is implementation defined, their 871 * number is stored in the MPAMIDR_EL1 register. 872 */ 873 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 874 case 7: 875 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 876 __fallthrough; 877 case 6: 878 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 879 __fallthrough; 880 case 5: 881 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 882 __fallthrough; 883 case 4: 884 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 885 __fallthrough; 886 case 3: 887 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 888 __fallthrough; 889 case 2: 890 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 891 __fallthrough; 892 case 1: 893 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 894 break; 895 } 896 } 897 898 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 899 { 900 u_register_t mpam_idr = read_mpamidr_el1(); 901 902 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 903 904 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 905 return; 906 } 907 908 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 909 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 910 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 911 912 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 913 case 7: 914 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 915 __fallthrough; 916 case 6: 917 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 918 __fallthrough; 919 case 5: 920 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 921 __fallthrough; 922 case 4: 923 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 924 __fallthrough; 925 case 3: 926 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 927 __fallthrough; 928 case 2: 929 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 930 __fallthrough; 931 case 1: 932 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 933 break; 934 } 935 } 936 937 /******************************************************************************* 938 * Save EL2 sysreg context 939 ******************************************************************************/ 940 void cm_el2_sysregs_context_save(uint32_t security_state) 941 { 942 u_register_t scr_el3 = read_scr(); 943 944 /* 945 * Always save the non-secure and realm EL2 context, only save the 946 * S-EL2 context if S-EL2 is enabled. 947 */ 948 if ((security_state != SECURE) || 949 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 950 cpu_context_t *ctx; 951 el2_sysregs_t *el2_sysregs_ctx; 952 953 ctx = cm_get_context(security_state); 954 assert(ctx != NULL); 955 956 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 957 958 el2_sysregs_context_save_common(el2_sysregs_ctx); 959 #if CTX_INCLUDE_MTE_REGS 960 el2_sysregs_context_save_mte(el2_sysregs_ctx); 961 #endif 962 if (is_feat_mpam_supported()) { 963 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 964 } 965 966 if (is_feat_fgt_supported()) { 967 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 968 } 969 970 if (is_feat_ecv_v2_supported()) { 971 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 972 read_cntpoff_el2()); 973 } 974 975 if (is_feat_vhe_supported()) { 976 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 977 read_contextidr_el2()); 978 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 979 read_ttbr1_el2()); 980 } 981 #if RAS_EXTENSION 982 el2_sysregs_context_save_ras(el2_sysregs_ctx); 983 #endif 984 985 if (is_feat_nv2_supported()) { 986 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 987 read_vncr_el2()); 988 } 989 990 if (is_feat_trf_supported()) { 991 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 992 } 993 994 if (is_feat_csv2_2_supported()) { 995 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 996 read_scxtnum_el2()); 997 } 998 999 if (is_feat_hcx_supported()) { 1000 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1001 } 1002 if (is_feat_tcr2_supported()) { 1003 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1004 } 1005 if (is_feat_sxpie_supported()) { 1006 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1007 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1008 } 1009 if (is_feat_s2pie_supported()) { 1010 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1011 } 1012 if (is_feat_sxpoe_supported()) { 1013 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1014 } 1015 } 1016 } 1017 1018 /******************************************************************************* 1019 * Restore EL2 sysreg context 1020 ******************************************************************************/ 1021 void cm_el2_sysregs_context_restore(uint32_t security_state) 1022 { 1023 u_register_t scr_el3 = read_scr(); 1024 1025 /* 1026 * Always restore the non-secure and realm EL2 context, only restore the 1027 * S-EL2 context if S-EL2 is enabled. 1028 */ 1029 if ((security_state != SECURE) || 1030 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1031 cpu_context_t *ctx; 1032 el2_sysregs_t *el2_sysregs_ctx; 1033 1034 ctx = cm_get_context(security_state); 1035 assert(ctx != NULL); 1036 1037 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1038 1039 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1040 #if CTX_INCLUDE_MTE_REGS 1041 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1042 #endif 1043 if (is_feat_mpam_supported()) { 1044 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1045 } 1046 1047 if (is_feat_fgt_supported()) { 1048 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1049 } 1050 1051 if (is_feat_ecv_v2_supported()) { 1052 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1053 CTX_CNTPOFF_EL2)); 1054 } 1055 1056 if (is_feat_vhe_supported()) { 1057 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1058 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1059 } 1060 #if RAS_EXTENSION 1061 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 1062 #endif 1063 1064 if (is_feat_nv2_supported()) { 1065 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1066 } 1067 if (is_feat_trf_supported()) { 1068 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1069 } 1070 1071 if (is_feat_csv2_2_supported()) { 1072 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1073 CTX_SCXTNUM_EL2)); 1074 } 1075 1076 if (is_feat_hcx_supported()) { 1077 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1078 } 1079 if (is_feat_tcr2_supported()) { 1080 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1081 } 1082 if (is_feat_sxpie_supported()) { 1083 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1084 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1085 } 1086 if (is_feat_s2pie_supported()) { 1087 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1088 } 1089 if (is_feat_sxpoe_supported()) { 1090 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1091 } 1092 } 1093 } 1094 #endif /* CTX_INCLUDE_EL2_REGS */ 1095 1096 /******************************************************************************* 1097 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1098 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1099 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1100 * cm_prepare_el3_exit function. 1101 ******************************************************************************/ 1102 void cm_prepare_el3_exit_ns(void) 1103 { 1104 #if CTX_INCLUDE_EL2_REGS 1105 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1106 assert(ctx != NULL); 1107 1108 /* Assert that EL2 is used. */ 1109 #if ENABLE_ASSERTIONS 1110 el3_state_t *state = get_el3state_ctx(ctx); 1111 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1112 #endif 1113 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1114 (el_implemented(2U) != EL_IMPL_NONE)); 1115 1116 /* 1117 * Currently some extensions are configured using 1118 * direct register updates. Therefore, do this here 1119 * instead of when setting up context. 1120 */ 1121 manage_extensions_nonsecure(0, ctx); 1122 1123 /* 1124 * Set the NS bit to be able to access the ICC_SRE_EL2 1125 * register when restoring context. 1126 */ 1127 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1128 1129 /* 1130 * Ensure the NS bit change is committed before the EL2/EL1 1131 * state restoration. 1132 */ 1133 isb(); 1134 1135 /* Restore EL2 and EL1 sysreg contexts */ 1136 cm_el2_sysregs_context_restore(NON_SECURE); 1137 cm_el1_sysregs_context_restore(NON_SECURE); 1138 cm_set_next_eret_context(NON_SECURE); 1139 #else 1140 cm_prepare_el3_exit(NON_SECURE); 1141 #endif /* CTX_INCLUDE_EL2_REGS */ 1142 } 1143 1144 /******************************************************************************* 1145 * The next four functions are used by runtime services to save and restore 1146 * EL1 context on the 'cpu_context' structure for the specified security 1147 * state. 1148 ******************************************************************************/ 1149 void cm_el1_sysregs_context_save(uint32_t security_state) 1150 { 1151 cpu_context_t *ctx; 1152 1153 ctx = cm_get_context(security_state); 1154 assert(ctx != NULL); 1155 1156 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1157 1158 #if IMAGE_BL31 1159 if (security_state == SECURE) 1160 PUBLISH_EVENT(cm_exited_secure_world); 1161 else 1162 PUBLISH_EVENT(cm_exited_normal_world); 1163 #endif 1164 } 1165 1166 void cm_el1_sysregs_context_restore(uint32_t security_state) 1167 { 1168 cpu_context_t *ctx; 1169 1170 ctx = cm_get_context(security_state); 1171 assert(ctx != NULL); 1172 1173 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1174 1175 #if IMAGE_BL31 1176 if (security_state == SECURE) 1177 PUBLISH_EVENT(cm_entering_secure_world); 1178 else 1179 PUBLISH_EVENT(cm_entering_normal_world); 1180 #endif 1181 } 1182 1183 /******************************************************************************* 1184 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1185 * given security state with the given entrypoint 1186 ******************************************************************************/ 1187 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1188 { 1189 cpu_context_t *ctx; 1190 el3_state_t *state; 1191 1192 ctx = cm_get_context(security_state); 1193 assert(ctx != NULL); 1194 1195 /* Populate EL3 state so that ERET jumps to the correct entry */ 1196 state = get_el3state_ctx(ctx); 1197 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1198 } 1199 1200 /******************************************************************************* 1201 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1202 * pertaining to the given security state 1203 ******************************************************************************/ 1204 void cm_set_elr_spsr_el3(uint32_t security_state, 1205 uintptr_t entrypoint, uint32_t spsr) 1206 { 1207 cpu_context_t *ctx; 1208 el3_state_t *state; 1209 1210 ctx = cm_get_context(security_state); 1211 assert(ctx != NULL); 1212 1213 /* Populate EL3 state so that ERET jumps to the correct entry */ 1214 state = get_el3state_ctx(ctx); 1215 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1216 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1217 } 1218 1219 /******************************************************************************* 1220 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1221 * pertaining to the given security state using the value and bit position 1222 * specified in the parameters. It preserves all other bits. 1223 ******************************************************************************/ 1224 void cm_write_scr_el3_bit(uint32_t security_state, 1225 uint32_t bit_pos, 1226 uint32_t value) 1227 { 1228 cpu_context_t *ctx; 1229 el3_state_t *state; 1230 u_register_t scr_el3; 1231 1232 ctx = cm_get_context(security_state); 1233 assert(ctx != NULL); 1234 1235 /* Ensure that the bit position is a valid one */ 1236 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1237 1238 /* Ensure that the 'value' is only a bit wide */ 1239 assert(value <= 1U); 1240 1241 /* 1242 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1243 * and set it to its new value. 1244 */ 1245 state = get_el3state_ctx(ctx); 1246 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1247 scr_el3 &= ~(1UL << bit_pos); 1248 scr_el3 |= (u_register_t)value << bit_pos; 1249 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1250 } 1251 1252 /******************************************************************************* 1253 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1254 * given security state. 1255 ******************************************************************************/ 1256 u_register_t cm_get_scr_el3(uint32_t security_state) 1257 { 1258 cpu_context_t *ctx; 1259 el3_state_t *state; 1260 1261 ctx = cm_get_context(security_state); 1262 assert(ctx != NULL); 1263 1264 /* Populate EL3 state so that ERET jumps to the correct entry */ 1265 state = get_el3state_ctx(ctx); 1266 return read_ctx_reg(state, CTX_SCR_EL3); 1267 } 1268 1269 /******************************************************************************* 1270 * This function is used to program the context that's used for exception 1271 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1272 * the required security state 1273 ******************************************************************************/ 1274 void cm_set_next_eret_context(uint32_t security_state) 1275 { 1276 cpu_context_t *ctx; 1277 1278 ctx = cm_get_context(security_state); 1279 assert(ctx != NULL); 1280 1281 cm_set_next_context(ctx); 1282 } 1283