1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52ifeq (${ARCH},aarch64) 53ifeq (${SPM_MM}, 0) 54ifeq (${ENABLE_RME}, 0) 55ifeq (${CTX_INCLUDE_FPREGS}, 0) 56 ENABLE_SME_FOR_NS := 2 57endif 58endif 59endif 60endif 61endif 62 63# enable unconditionally for all builds 64ifeq (${ARCH}, aarch64) 65ifeq (${ENABLE_RME},0) 66 ENABLE_BRBE_FOR_NS := 2 67endif 68endif 69ENABLE_TRBE_FOR_NS := 2 70ENABLE_SYS_REG_TRACE_FOR_NS := 2 71ENABLE_FEAT_CSV2_2 := 2 72ENABLE_FEAT_PAN := 2 73ENABLE_FEAT_VHE := 2 74CTX_INCLUDE_NEVE_REGS := 2 75ENABLE_FEAT_SEL2 := 2 76ENABLE_TRF_FOR_NS := 2 77ENABLE_FEAT_ECV := 2 78ENABLE_FEAT_FGT := 2 79ENABLE_FEAT_TCR2 := 2 80endif 81 82# The FVP platform depends on this macro to build with correct GIC driver. 83$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 84 85# Pass FVP_CLUSTER_COUNT to the build system. 86$(eval $(call add_define,FVP_CLUSTER_COUNT)) 87 88# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 89$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 90 91# Pass FVP_MAX_PE_PER_CPU to the build system. 92$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 93 94# Pass FVP_GICR_REGION_PROTECTION to the build system. 95$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 96 97# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 98# choose the CCI driver , else the CCN driver 99ifeq ($(FVP_CLUSTER_COUNT), 0) 100$(error "Incorrect cluster count specified for FVP port") 101else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 102FVP_INTERCONNECT_DRIVER := FVP_CCI 103else 104FVP_INTERCONNECT_DRIVER := FVP_CCN 105endif 106 107$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 108 109# Choose the GIC sources depending upon the how the FVP will be invoked 110ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 111 112# The GIC model (GIC-600 or GIC-500) will be detected at runtime 113GICV3_SUPPORT_GIC600 := 1 114GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 115 116# Include GICv3 driver files 117include drivers/arm/gic/v3/gicv3.mk 118 119FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 120 plat/common/plat_gicv3.c \ 121 plat/arm/common/arm_gicv3.c 122 123 ifeq ($(filter 1,${RESET_TO_BL2} \ 124 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 125 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 126 endif 127 128else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 129 130# No GICv4 extension 131GIC_ENABLE_V4_EXTN := 0 132$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 133 134# Include GICv2 driver files 135include drivers/arm/gic/v2/gicv2.mk 136 137FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 138 plat/common/plat_gicv2.c \ 139 plat/arm/common/arm_gicv2.c 140 141FVP_DT_PREFIX := fvp-base-gicv2-psci 142else 143$(error "Incorrect GIC driver chosen on FVP port") 144endif 145 146ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 147FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 148else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 149FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 150 plat/arm/common/arm_ccn.c 151else 152$(error "Incorrect CCN driver chosen on FVP port") 153endif 154 155FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 156 plat/arm/board/fvp/fvp_security.c \ 157 plat/arm/common/arm_tzc400.c 158 159 160PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 161 -Iinclude/lib/psa 162 163 164PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 165 166FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 167 168ifeq (${ARCH}, aarch64) 169 170# select a different set of CPU files, depending on whether we compile for 171# hardware assisted coherency cores or not 172ifeq (${HW_ASSISTED_COHERENCY}, 0) 173# Cores used without DSU 174 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 175 lib/cpus/aarch64/cortex_a53.S \ 176 lib/cpus/aarch64/cortex_a57.S \ 177 lib/cpus/aarch64/cortex_a72.S \ 178 lib/cpus/aarch64/cortex_a73.S 179else 180# Cores used with DSU only 181 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 182 # AArch64-only cores 183 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 184 lib/cpus/aarch64/cortex_a76ae.S \ 185 lib/cpus/aarch64/cortex_a77.S \ 186 lib/cpus/aarch64/cortex_a78.S \ 187 lib/cpus/aarch64/neoverse_n_common.S \ 188 lib/cpus/aarch64/neoverse_n1.S \ 189 lib/cpus/aarch64/neoverse_n2.S \ 190 lib/cpus/aarch64/neoverse_e1.S \ 191 lib/cpus/aarch64/neoverse_v1.S \ 192 lib/cpus/aarch64/neoverse_v2.S \ 193 lib/cpus/aarch64/cortex_a78_ae.S \ 194 lib/cpus/aarch64/cortex_a510.S \ 195 lib/cpus/aarch64/cortex_a710.S \ 196 lib/cpus/aarch64/cortex_a715.S \ 197 lib/cpus/aarch64/cortex_x3.S \ 198 lib/cpus/aarch64/cortex_a65.S \ 199 lib/cpus/aarch64/cortex_a65ae.S \ 200 lib/cpus/aarch64/cortex_a78c.S \ 201 lib/cpus/aarch64/cortex_hayes.S \ 202 lib/cpus/aarch64/cortex_hunter.S \ 203 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 204 lib/cpus/aarch64/cortex_x2.S \ 205 lib/cpus/aarch64/neoverse_poseidon.S 206 endif 207 # AArch64/AArch32 cores 208 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 209 lib/cpus/aarch64/cortex_a75.S 210endif 211 212else 213FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 214 lib/cpus/aarch32/cortex_a57.S 215endif 216 217BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 218 drivers/arm/sp805/sp805.c \ 219 drivers/delay_timer/delay_timer.c \ 220 drivers/io/io_semihosting.c \ 221 lib/semihosting/semihosting.c \ 222 lib/semihosting/${ARCH}/semihosting_call.S \ 223 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 224 plat/arm/board/fvp/fvp_bl1_setup.c \ 225 plat/arm/board/fvp/fvp_err.c \ 226 plat/arm/board/fvp/fvp_io_storage.c \ 227 ${FVP_CPU_LIBS} \ 228 ${FVP_INTERCONNECT_SOURCES} 229 230ifeq (${USE_SP804_TIMER},1) 231BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 232else 233BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 234endif 235 236 237BL2_SOURCES += drivers/arm/sp805/sp805.c \ 238 drivers/io/io_semihosting.c \ 239 lib/utils/mem_region.c \ 240 lib/semihosting/semihosting.c \ 241 lib/semihosting/${ARCH}/semihosting_call.S \ 242 plat/arm/board/fvp/fvp_bl2_setup.c \ 243 plat/arm/board/fvp/fvp_err.c \ 244 plat/arm/board/fvp/fvp_io_storage.c \ 245 plat/arm/common/arm_nor_psci_mem_protect.c \ 246 ${FVP_SECURITY_SOURCES} 247 248 249ifeq (${COT_DESC_IN_DTB},1) 250BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 251endif 252 253ifeq (${ENABLE_RME},1) 254BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 255 256BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 257 plat/arm/board/fvp/fvp_realm_attest_key.c 258 259# FVP platform does not support RSS, but it can leverage RSS APIs to 260# provide hardcoded token/key on request. 261BL31_SOURCES += lib/psa/delegated_attestation.c 262 263endif 264 265ifeq (${ENABLE_FEAT_RNG_TRAP},1) 266BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 267endif 268 269ifeq (${RESET_TO_BL2},1) 270BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 271 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 272 ${FVP_CPU_LIBS} \ 273 ${FVP_INTERCONNECT_SOURCES} 274endif 275 276ifeq (${USE_SP804_TIMER},1) 277BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 278endif 279 280BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 281 ${FVP_SECURITY_SOURCES} 282 283ifeq (${USE_SP804_TIMER},1) 284BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 285endif 286 287BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 288 drivers/arm/smmu/smmu_v3.c \ 289 drivers/delay_timer/delay_timer.c \ 290 drivers/cfi/v2m/v2m_flash.c \ 291 lib/utils/mem_region.c \ 292 plat/arm/board/fvp/fvp_bl31_setup.c \ 293 plat/arm/board/fvp/fvp_console.c \ 294 plat/arm/board/fvp/fvp_pm.c \ 295 plat/arm/board/fvp/fvp_topology.c \ 296 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 297 plat/arm/common/arm_nor_psci_mem_protect.c \ 298 ${FVP_CPU_LIBS} \ 299 ${FVP_GIC_SOURCES} \ 300 ${FVP_INTERCONNECT_SOURCES} \ 301 ${FVP_SECURITY_SOURCES} 302 303# Support for fconf in BL31 304# Added separately from the above list for better readability 305ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 306BL31_SOURCES += lib/fconf/fconf.c \ 307 lib/fconf/fconf_dyn_cfg_getter.c \ 308 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 309 310BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 311 312ifeq (${SEC_INT_DESC_IN_FCONF},1) 313BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 314endif 315 316endif 317 318ifeq (${USE_SP804_TIMER},1) 319BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 320else 321BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 322endif 323 324# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 325ifdef UNIX_MK 326FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 327FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 328 ${PLAT}_fw_config.dts \ 329 ${PLAT}_tb_fw_config.dts \ 330 ${PLAT}_soc_fw_config.dts \ 331 ${PLAT}_nt_fw_config.dts \ 332 ) 333 334FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 335FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 336FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 337FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 338 339ifeq (${SPD},tspd) 340FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 341FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 342 343# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 344$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 345endif 346 347ifeq (${SPD},spmd) 348 349ifeq ($(ARM_SPMC_MANIFEST_DTS),) 350ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 351endif 352 353FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 354FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 355 356# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 357$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 358endif 359 360# Add the FW_CONFIG to FIP and specify the same to certtool 361$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 362# Add the TB_FW_CONFIG to FIP and specify the same to certtool 363$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 364# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 366# Add the NT_FW_CONFIG to FIP and specify the same to certtool 367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 368 369FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 370$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 371 372# Add the HW_CONFIG to FIP and specify the same to certtool 373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 374endif 375 376# Enable dynamic mitigation support by default 377DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 378 379ifneq (${ENABLE_FEAT_AMU},0) 380BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 381 lib/cpus/aarch64/cpuamu_helpers.S 382 383ifeq (${HW_ASSISTED_COHERENCY}, 1) 384BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 385 lib/cpus/aarch64/neoverse_n1_pubsub.c 386endif 387endif 388 389ifeq (${RAS_EXTENSION},1) 390BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 391endif 392 393ifneq (${ENABLE_STACK_PROTECTOR},0) 394PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 395endif 396 397ifeq (${ARCH},aarch32) 398 NEED_BL32 := yes 399endif 400 401# Enable the dynamic translation tables library. 402ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 403 ifeq (${ARCH},aarch32) 404 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 405 else # AArch64 406 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 407 endif 408endif 409 410ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 411 ifeq (${ARCH},aarch32) 412 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 413 else # AArch64 414 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 415 ifeq (${SPD},tspd) 416 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 417 endif 418 endif 419endif 420 421ifeq (${USE_DEBUGFS},1) 422 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 423endif 424 425# Add support for platform supplied linker script for BL31 build 426$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 427 428ifneq (${RESET_TO_BL2}, 0) 429 override BL1_SOURCES = 430endif 431 432# RSS is not supported on FVP right now. Thus, we use the mocked version 433# of the provided PSA APIs. They return with success and hard-coded token/key. 434PLAT_RSS_NOT_SUPPORTED := 1 435 436# Include Measured Boot makefile before any Crypto library makefile. 437# Crypto library makefile may need default definitions of Measured Boot build 438# flags present in Measured Boot makefile. 439ifeq (${MEASURED_BOOT},1) 440 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 441 $(info Including ${RSS_MEASURED_BOOT_MK}) 442 include ${RSS_MEASURED_BOOT_MK} 443 444 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 445 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 446 endif 447 448 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 449 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 450endif 451 452include plat/arm/board/common/board_common.mk 453include plat/arm/common/arm_common.mk 454 455ifeq (${MEASURED_BOOT},1) 456BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 457 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 458 lib/psa/measured_boot.c 459 460BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 461 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 462 lib/psa/measured_boot.c 463 464# Even though RSS is not supported on FVP (see above), we support overriding 465# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 466# the code to detect any build regressions. The resulting firmware will not be 467# functional. 468ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 469 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 470 include drivers/arm/rss/rss_comms.mk 471 BL1_SOURCES += ${RSS_COMMS_SOURCES} 472 BL2_SOURCES += ${RSS_COMMS_SOURCES} 473 BL31_SOURCES += ${RSS_COMMS_SOURCES} 474 475 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 476 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 477 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 478endif 479 480endif 481 482ifeq (${DRTM_SUPPORT}, 1) 483BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 484 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 485 plat/arm/board/fvp/fvp_drtm_err.c \ 486 plat/arm/board/fvp/fvp_drtm_measurement.c \ 487 plat/arm/board/fvp/fvp_drtm_stub.c \ 488 plat/arm/common/arm_dyn_cfg.c \ 489 plat/arm/board/fvp/fvp_err.c 490endif 491 492ifeq (${TRUSTED_BOARD_BOOT}, 1) 493BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 494BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 495 496# FVP being a development platform, enable capability to disable Authentication 497# dynamically if TRUSTED_BOARD_BOOT is set. 498DYN_DISABLE_AUTH := 1 499endif 500 501ifeq (${SPMC_AT_EL3}, 1) 502PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 503endif 504 505PSCI_OS_INIT_MODE := 1 506