1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 57 entrypoint) or 1 (CPU reset to BL2 entrypoint). 58 The default value is 0. 59 60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 62 true in a 4-world system where RESET_TO_BL2 is 0. 63 64- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 66 67- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 69 the RW sections in RAM, while leaving the RO sections in place. This option 70 enable this use-case. For now, this option is only supported 71 when RESET_TO_BL2 is set to '1'. 72 73- ``BL31``: This is an optional build option which specifies the path to 74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 75 be built. 76 77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 79 this file name will be used to save the key. 80 81- ``BL32``: This is an optional build option which specifies the path to 82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 83 be built. 84 85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 86 Trusted OS Extra1 image for the ``fip`` target. 87 88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 89 Trusted OS Extra2 image for the ``fip`` target. 90 91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 93 this file name will be used to save the key. 94 95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 96 ``fip`` target in case TF-A BL2 is used. 97 98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 100 this file name will be used to save the key. 101 102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 104 If enabled, it is needed to use a compiler that supports the option 105 ``-mbranch-protection``. Selects the branch protection features to use: 106- 0: Default value turns off all types of branch protection 107- 1: Enables all types of branch protection features 108- 2: Return address signing to its standard level 109- 3: Extend the signing to include leaf functions 110- 4: Turn on branch target identification mechanism 111 112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 113 and resulting PAuth/BTI features. 114 115 +-------+--------------+-------+-----+ 116 | Value | GCC option | PAuth | BTI | 117 +=======+==============+=======+=====+ 118 | 0 | none | N | N | 119 +-------+--------------+-------+-----+ 120 | 1 | standard | Y | Y | 121 +-------+--------------+-------+-----+ 122 | 2 | pac-ret | Y | N | 123 +-------+--------------+-------+-----+ 124 | 3 | pac-ret+leaf | Y | N | 125 +-------+--------------+-------+-----+ 126 | 4 | bti | N | Y | 127 +-------+--------------+-------+-----+ 128 129 This option defaults to 0. 130 Note that Pointer Authentication is enabled for Non-secure world 131 irrespective of the value of this option if the CPU supports it. 132 133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 134 compilation of each build. It must be set to a C string (including quotes 135 where applicable). Defaults to a string that contains the time and date of 136 the compilation. 137 138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 139 build to be uniquely identified. Defaults to the current git commit id. 140 141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 142 143- ``CFLAGS``: Extra user options appended on the compiler's command line in 144 addition to the options set by the build system. 145 146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 147 release several CPUs out of reset. It can take either 0 (several CPUs may be 148 brought up) or 1 (only one CPU will ever be brought up during cold reset). 149 Default is 0. If the platform always brings up a single CPU, there is no 150 need to distinguish between primary and secondary CPUs and the boot path can 151 be optimised. The ``plat_is_my_cpu_primary()`` and 152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 153 to be implemented in this case. 154 155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 156 Defaults to ``tbbr``. 157 158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 159 register state when an unexpected exception occurs during execution of 160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 161 this is only enabled for a debug build of the firmware. 162 163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 164 certificate generation tool to create new keys in case no valid keys are 165 present or specified. Allowed options are '0' or '1'. Default is '1'. 166 167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 168 the AArch32 system registers to be included when saving and restoring the 169 CPU context. The option must be set to 0 for AArch64-only platforms (that 170 is on hardware that does not implement AArch32, or at least not at EL1 and 171 higher ELs). Default value is 1. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 178 registers in cpu context. This must be enabled, if the platform wants to use 179 this feature in the Secure world and MTE is enabled at ELX. This flag can 180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 181 Default value is 0. 182 183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 184 registers to be saved/restored when entering/exiting an EL2 execution 185 context. This flag can take values 0 to 2, to align with the 186 ``FEATURE_DETECTION`` mechanism. Default value is 0. 187 188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 190 to be included when saving and restoring the CPU context as part of world 191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 192 mechanism. Default value is 0. 193 194 Note that Pointer Authentication is enabled for Non-secure world irrespective 195 of the value of this flag if the CPU supports it. 196 197- ``DEBUG``: Chooses between a debug and release build. It can take either 0 198 (release) or 1 (debug) as values. 0 is the default. 199 200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 201 authenticated decryption algorithm to be used to decrypt firmware/s during 202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 203 this flag is ``none`` to disable firmware decryption which is an optional 204 feature as per TBBR. 205 206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 207 of the binary image. If set to 1, then only the ELF image is built. 208 0 is the default. 209 210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 213 check the latest Arm ARM. 214 215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 216 Board Boot authentication at runtime. This option is meant to be enabled only 217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 218 flag has to be enabled. 0 is the default. 219 220- ``E``: Boolean option to make warnings into errors. Default is 1. 221 222 When specifying higher warnings levels (``W=1`` and higher), this option 223 defaults to 0. This is done to encourage contributors to use them, as they 224 are expected to produce warnings that would otherwise fail the build. New 225 contributions are still expected to build with ``W=0`` and ``E=1`` (the 226 default). 227 228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 229 the normal boot flow. It must specify the entry point address of the EL3 230 payload. Please refer to the "Booting an EL3 payload" section for more 231 details. 232 233- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 234 (also known as group 1 counters). These are implementation-defined counters, 235 and as such require additional platform configuration. Default is 0. 236 237- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 238 allows platforms with auxiliary counters to describe them via the 239 ``HW_CONFIG`` device tree blob. Default is 0. 240 241- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 242 are compiled out. For debug builds, this option defaults to 1, and calls to 243 ``assert()`` are left in place. For release builds, this option defaults to 0 244 and calls to ``assert()`` function are compiled out. This option can be set 245 independently of ``DEBUG``. It can also be used to hide any auxiliary code 246 that is only required for the assertion and does not fit in the assertion 247 itself. 248 249- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 250 dumps or not. It is supported in both AArch64 and AArch32. However, in 251 AArch32 the format of the frame records are not defined in the AAPCS and they 252 are defined by the implementation. This implementation of backtrace only 253 supports the format used by GCC when T32 interworking is disabled. For this 254 reason enabling this option in AArch32 will force the compiler to only 255 generate A32 code. This option is enabled by default only in AArch64 debug 256 builds, but this behaviour can be overridden in each platform's Makefile or 257 in the build command line. 258 259- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 260 extensions. This flag can take the values 0 to 2, to align with the 261 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 262 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 263 and this option can be used to enable this feature on those systems as well. 264 This flag can take the values 0 to 2, the default is 0. 265 266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 268 onwards. This flag can take the values 0 to 2, to align with the 269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 270 271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 274 optional feature available on Arm v8.0 onwards. This flag can take values 275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 276 Default value is ``0``. 277 278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 281 and upwards. This flag can take the values 0 to 2, to align with the 282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 283 284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 286 Physical Offset register) during EL2 to EL3 context save/restore operations. 287 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 289 mechanism. Default value is ``0``. 290 291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 293 Read Trap Register) during EL2 to EL3 context save/restore operations. 294 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 296 mechanism. Default value is ``0``. 297 298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 301 mandatory architectural feature and is enabled from v8.7 and upwards. This 302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 303 mechanism. Default value is ``0``. 304 305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 307 permission fault for any privileged data access from EL1/EL2 to virtual 308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 309 mandatory architectural feature and is enabled from v8.1 and upwards. This 310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 311 mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 316 mechanism. Default value is ``0``. 317 318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 319 extension. This feature is only supported in AArch64 state. This flag can 320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 322 Armv8.5 onwards. 323 324- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 325 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 326 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 327 later CPUs. It is enabled from v8.5 and upwards and if needed can be 328 overidden from platforms explicitly. 329 330- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 331 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 332 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 333 mechanism. Default is ``0``. 334 335- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 336 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 337 available on Arm v8.6. This flag can take values 0 to 2, to align with the 338 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 339 340 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 341 delayed by the amount of value in ``TWED_DELAY``. 342 343- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 344 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 345 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 346 architectural feature and is enabled from v8.1 and upwards. It can take 347 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 348 Default value is ``0``. 349 350- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 351 allow access to TCR2_EL2 (extended translation control) from EL2 as 352 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 353 mandatory architectural feature and is enabled from v8.9 and upwards. This 354 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 355 mechanism. Default value is ``0``. 356 357- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 358 support in GCC for TF-A. This option is currently only supported for 359 AArch64. Default is 0. 360 361- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 362 feature. MPAM is an optional Armv8.4 extension that enables various memory 363 system components and resources to define partitions; software running at 364 various ELs can assign themselves to desired partition to control their 365 performance aspects. 366 367 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 368 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 369 access their own MPAM registers without trapping into EL3. This option 370 doesn't make use of partitioning in EL3, however. Platform initialisation 371 code should configure and use partitions in EL3 as required. This option 372 defaults to ``0``. 373 374- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 375 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 376 firmware to detect and limit high activity events to assist in SoC processor 377 power domain dynamic power budgeting and limit the triggering of whole-rail 378 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 379 380- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 381 allows platforms with cores supporting MPMM to describe them via the 382 ``HW_CONFIG`` device tree blob. Default is 0. 383 384- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 385 support within generic code in TF-A. This option is currently only supported 386 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 387 in BL32 (SP_min) for AARCH32. Default is 0. 388 389- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 390 Measurement Framework(PMF). Default is 0. 391 392- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 393 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 394 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 395 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 396 software. 397 398- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 399 Management Extension. This flag can take the values 0 to 2, to align with 400 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 401 an experimental feature. 402 403- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 404 instrumentation which injects timestamp collection points into TF-A to 405 allow runtime performance to be measured. Currently, only PSCI is 406 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 407 as well. Default is 0. 408 409- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 410 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 411 registers so are enabled together. Using this option without 412 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 413 world to trap to EL3. SME is an optional architectural feature for AArch64 414 and TF-A support is experimental. At this time, this build option cannot be 415 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 416 build with these options will fail. This flag can take the values 0 to 2, to 417 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 418 419- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 420 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 421 must also be set to use this. If enabling this, the secure world MUST 422 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 423 no data is leaked to non-secure world. This is experimental. Default is 0. 424 425- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 426 extensions. This is an optional architectural feature for AArch64. 427 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 428 mechanism. The default is 2 but is automatically disabled when the target 429 architecture is AArch32. 430 431- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 432 (SVE) for the Non-secure world only. SVE is an optional architectural feature 433 for AArch64. Note that when SVE is enabled for the Non-secure world, access 434 to SIMD and floating-point functionality from the Secure world is disabled by 435 default and controlled with ENABLE_SVE_FOR_SWD. 436 This is to avoid corruption of the Non-secure world data in the Z-registers 437 which are aliased by the SIMD and FP registers. The build option is not 438 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 439 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 440 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 441 since SME encompasses SVE. At this time, this build option cannot be used on 442 systems that have SPM_MM enabled. 443 444- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 445 SVE is an optional architectural feature for AArch64. Note that this option 446 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it 447 is automatically disabled when the target architecture is AArch32. 448 449- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 450 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 451 default value is set to "none". "strong" is the recommended stack protection 452 level if this feature is desired. "none" disables the stack protection. For 453 all values other than "none", the ``plat_get_stack_protector_canary()`` 454 platform hook needs to be implemented. The value is passed as the last 455 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 456 457- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 458 flag depends on ``DECRYPTION_SUPPORT`` build flag. 459 460- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 461 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 462 463- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 464 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 465 on ``DECRYPTION_SUPPORT`` build flag. 466 467- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 468 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 469 build flag. 470 471- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 472 deprecated platform APIs, helper functions or drivers within Trusted 473 Firmware as error. It can take the value 1 (flag the use of deprecated 474 APIs as error) or 0. The default is 0. 475 476- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 477 targeted at EL3. When set ``0`` (default), no exceptions are expected or 478 handled at EL3, and a panic will result. The exception to this rule is when 479 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 480 occuring during normal world execution, are trapped to EL3. Any exception 481 trapped during secure world execution are trapped to the SPMC. This is 482 supported only for AArch64 builds. 483 484- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 485 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 486 Default value is 40 (LOG_LEVEL_INFO). 487 488- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 489 injection from lower ELs, and this build option enables lower ELs to use 490 Error Records accessed via System Registers to inject faults. This is 491 applicable only to AArch64 builds. 492 493 This feature is intended for testing purposes only, and is advisable to keep 494 disabled for production images. 495 496- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 497 detection mechanism. It detects whether the Architectural features enabled 498 through feature specific build flags are supported by the PE or not by 499 validating them either at boot phase or at runtime based on the value 500 possessed by the feature flag (0 to 2) and report error messages at an early 501 stage. 502 503 This prevents and benefits us from EL3 runtime exceptions during context save 504 and restore routines guarded by these build flags. Henceforth validating them 505 before their usage provides more control on the actions taken under them. 506 507 The mechanism permits the build flags to take values 0, 1 or 2 and 508 evaluates them accordingly. 509 510 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 511 512 :: 513 514 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 515 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 516 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 517 518 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 519 0, feature is disabled statically during compilation. If it is defined as 1, 520 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 521 implemented by the PE, a hard panic is generated. Finally, if the flag is set 522 to 2, feature is validated at runtime. 523 524 Note that the entire implementation is divided into two phases, wherein as 525 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 526 supported and is planned to be handled explicilty in phase-2 implementation. 527 528 FEATURE_DETECTION macro is disabled by default, and is currently an 529 experimental procedure. Platforms can explicitly make use of this by 530 mechanism, by enabling it to validate whether they have set their build flags 531 properly at an early phase. 532 533- ``FIP_NAME``: This is an optional build option which specifies the FIP 534 filename for the ``fip`` target. Default is ``fip.bin``. 535 536- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 537 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 538 539- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 540 541 :: 542 543 0: Encryption is done with Secret Symmetric Key (SSK) which is common 544 for a class of devices. 545 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 546 unique per device. 547 548 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 549 550- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 551 tool to create certificates as per the Chain of Trust described in 552 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 553 include the certificates in the FIP and FWU_FIP. Default value is '0'. 554 555 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 556 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 557 the corresponding certificates, and to include those certificates in the 558 FIP and FWU_FIP. 559 560 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 561 images will not include support for Trusted Board Boot. The FIP will still 562 include the corresponding certificates. This FIP can be used to verify the 563 Chain of Trust on the host machine through other mechanisms. 564 565 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 566 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 567 will not include the corresponding certificates, causing a boot failure. 568 569- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 570 inherent support for specific EL3 type interrupts. Setting this build option 571 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 572 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 573 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 574 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 575 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 576 the Secure Payload interrupts needs to be synchronously handed over to Secure 577 EL1 for handling. The default value of this option is ``0``, which means the 578 Group 0 interrupts are assumed to be handled by Secure EL1. 579 580- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 581 Interrupts, resulting from errors in NS world, will be always trapped in 582 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 583 will be trapped in the current exception level (or in EL1 if the current 584 exception level is EL0). 585 586- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 587 software operations are required for CPUs to enter and exit coherency. 588 However, newer systems exist where CPUs' entry to and exit from coherency 589 is managed in hardware. Such systems require software to only initiate these 590 operations, and the rest is managed in hardware, minimizing active software 591 management. In such systems, this boolean option enables TF-A to carry out 592 build and run-time optimizations during boot and power management operations. 593 This option defaults to 0 and if it is enabled, then it implies 594 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 595 596 If this flag is disabled while the platform which TF-A is compiled for 597 includes cores that manage coherency in hardware, then a compilation error is 598 generated. This is based on the fact that a system cannot have, at the same 599 time, cores that manage coherency in hardware and cores that don't. In other 600 words, a platform cannot have, at the same time, cores that require 601 ``HW_ASSISTED_COHERENCY=1`` and cores that require 602 ``HW_ASSISTED_COHERENCY=0``. 603 604 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 605 translation library (xlat tables v2) must be used; version 1 of translation 606 library is not supported. 607 608- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 609 bottom, higher addresses at the top. This build flag can be set to '1' to 610 invert this behavior. Lower addresses will be printed at the top and higher 611 addresses at the bottom. 612 613- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 614 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 615 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 616 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 617 images. 618 619- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 620 used for generating the PKCS keys and subsequent signing of the certificate. 621 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 622 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 623 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 624 compatibility. The default value of this flag is ``rsa`` which is the TBBR 625 compliant PKCS#1 RSA 2.1 scheme. 626 627- ``KEY_SIZE``: This build flag enables the user to select the key size for 628 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 629 depend on the chosen algorithm and the cryptographic module. 630 631 +---------------------------+------------------------------------+ 632 | KEY_ALG | Possible key sizes | 633 +===========================+====================================+ 634 | rsa | 1024 , 2048 (default), 3072, 4096* | 635 +---------------------------+------------------------------------+ 636 | ecdsa | unavailable | 637 +---------------------------+------------------------------------+ 638 | ecdsa-brainpool-regular | unavailable | 639 +---------------------------+------------------------------------+ 640 | ecdsa-brainpool-twisted | unavailable | 641 +---------------------------+------------------------------------+ 642 643 644 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 645 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 646 647- ``HASH_ALG``: This build flag enables the user to select the secure hash 648 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 649 The default value of this flag is ``sha256``. 650 651- ``LDFLAGS``: Extra user options appended to the linkers' command line in 652 addition to the one set by the build system. 653 654- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 655 output compiled into the build. This should be one of the following: 656 657 :: 658 659 0 (LOG_LEVEL_NONE) 660 10 (LOG_LEVEL_ERROR) 661 20 (LOG_LEVEL_NOTICE) 662 30 (LOG_LEVEL_WARNING) 663 40 (LOG_LEVEL_INFO) 664 50 (LOG_LEVEL_VERBOSE) 665 666 All log output up to and including the selected log level is compiled into 667 the build. The default value is 40 in debug builds and 20 in release builds. 668 669- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 670 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 671 provide trust that the code taking the measurements and recording them has 672 not been tampered with. 673 674 This option defaults to 0. 675 676- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 677 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 678 the measurements and recording them as per `PSA DRTM specification`_. For 679 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 680 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 681 should have mechanism to authenticate BL31. This is an experimental feature. 682 683 This option defaults to 0. 684 685- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 686 specifies the file that contains the Non-Trusted World private key in PEM 687 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 688 689- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 690 optional. It is only needed if the platform makefile specifies that it 691 is required in order to build the ``fwu_fip`` target. 692 693- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 694 contents upon world switch. It can take either 0 (don't save and restore) or 695 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 696 wants the timer registers to be saved and restored. 697 698- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 699 for the BL image. It can be either 0 (include) or 1 (remove). The default 700 value is 0. 701 702- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 703 the underlying hardware is not a full PL011 UART but a minimally compliant 704 generic UART, which is a subset of the PL011. The driver will not access 705 any register that is not part of the SBSA generic UART specification. 706 Default value is 0 (a full PL011 compliant UART is present). 707 708- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 709 must be subdirectory of any depth under ``plat/``, and must contain a 710 platform makefile named ``platform.mk``. For example, to build TF-A for the 711 Arm Juno board, select PLAT=juno. 712 713- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 714 instead of the normal boot flow. When defined, it must specify the entry 715 point address for the preloaded BL33 image. This option is incompatible with 716 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 717 over ``PRELOADED_BL33_BASE``. 718 719- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 720 vector address can be programmed or is fixed on the platform. It can take 721 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 722 programmable reset address, it is expected that a CPU will start executing 723 code directly at the right address, both on a cold and warm reset. In this 724 case, there is no need to identify the entrypoint on boot and the boot path 725 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 726 does not need to be implemented in this case. 727 728- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 729 possible for the PSCI power-state parameter: original and extended State-ID 730 formats. This flag if set to 1, configures the generic PSCI layer to use the 731 extended format. The default value of this flag is 0, which means by default 732 the original power-state format is used by the PSCI implementation. This flag 733 should be specified by the platform makefile and it governs the return value 734 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 735 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 736 set to 1 as well. 737 738- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 739 OS-initiated mode. This option defaults to 0. 740 741- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features 742 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 743 or later CPUs. This flag can take the values 0 to 2, to align with the 744 ``FEATURE_DETECTION`` mechanism. 745 746 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be 747 set to ``1``. 748 749 This option is disabled by default. 750 751- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 752 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 753 entrypoint) or 1 (CPU reset to BL31 entrypoint). 754 The default value is 0. 755 756- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting 757 this additional option guarantees that the input registers are not cleared 758 therefore allowing parameters to be passed to the BL31 entrypoint. 759 The default value is 0. 760 761- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 762 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 763 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 764 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 765 766- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 767 file that contains the ROT private key in PEM format and enforces public key 768 hash generation. If ``SAVE_KEYS=1``, this 769 file name will be used to save the key. 770 771- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 772 certificate generation tool to save the keys used to establish the Chain of 773 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 774 775- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 776 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 777 target. 778 779- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 780 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 781 this file name will be used to save the key. 782 783- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 784 optional. It is only needed if the platform makefile specifies that it 785 is required in order to build the ``fwu_fip`` target. 786 787- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 788 Delegated Exception Interface to BL31 image. This defaults to ``0``. 789 790 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 791 set to ``1``. 792 793- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 794 isolated on separate memory pages. This is a trade-off between security and 795 memory usage. See "Isolating code and read-only data on separate memory 796 pages" section in :ref:`Firmware Design`. This flag is disabled by default 797 and affects all BL images. 798 799- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 800 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 801 allocated in RAM discontiguous from the loaded firmware image. When set, the 802 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 803 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 804 sections are placed in RAM immediately following the loaded firmware image. 805 806- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 807 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 808 discontiguous from loaded firmware images. When set, the platform need to 809 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 810 flag is disabled by default and NOLOAD sections are placed in RAM immediately 811 following the loaded firmware image. 812 813- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 814 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 815 UEFI+ACPI this can provide a certain amount of OS forward compatibility 816 with newer platforms that aren't ECAM compliant. 817 818- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 819 This build option is only valid if ``ARCH=aarch64``. The value should be 820 the path to the directory containing the SPD source, relative to 821 ``services/spd/``; the directory is expected to contain a makefile called 822 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 823 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 824 cannot be enabled when the ``SPM_MM`` option is enabled. 825 826- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 827 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 828 execution in BL1 just before handing over to BL31. At this point, all 829 firmware images have been loaded in memory, and the MMU and caches are 830 turned off. Refer to the "Debugging options" section for more details. 831 832- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 833 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 834 component runs at the EL3 exception level. The default value is ``0`` ( 835 disabled). This configuration supports pre-Armv8.4 platforms (aka not 836 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 837 838- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 839 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 840 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 841 mechanism should be used. 842 843- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 844 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 845 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 846 extension. This is the default when enabling the SPM Dispatcher. When 847 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 848 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 849 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 850 extension). 851 852- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 853 Partition Manager (SPM) implementation. The default value is ``0`` 854 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 855 enabled (``SPD=spmd``). 856 857- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 858 description of secure partitions. The build system will parse this file and 859 package all secure partition blobs into the FIP. This file is not 860 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 861 862- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 863 secure interrupts (caught through the FIQ line). Platforms can enable 864 this directive if they need to handle such interruption. When enabled, 865 the FIQ are handled in monitor mode and non secure world is not allowed 866 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 867 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 868 869- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 870 Platforms can configure this if they need to lower the hardware 871 limit, for example due to asymmetric configuration or limitations of 872 software run at lower ELs. The default is the architectural maximum 873 of 2048 which should be suitable for most configurations, the 874 hardware will limit the effective VL to the maximum physically supported 875 VL. 876 877- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 878 Random Number Generator Interface to BL31 image. This defaults to ``0``. 879 880- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 881 Boot feature. When set to '1', BL1 and BL2 images include support to load 882 and verify the certificates and images in a FIP, and BL1 includes support 883 for the Firmware Update. The default value is '0'. Generation and inclusion 884 of certificates in the FIP and FWU_FIP depends upon the value of the 885 ``GENERATE_COT`` option. 886 887 .. warning:: 888 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 889 already exist in disk, they will be overwritten without further notice. 890 891- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 892 specifies the file that contains the Trusted World private key in PEM 893 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 894 895- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 896 synchronous, (see "Initializing a BL32 Image" section in 897 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 898 synchronous method) or 1 (BL32 is initialized using asynchronous method). 899 Default is 0. 900 901- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 902 routing model which routes non-secure interrupts asynchronously from TSP 903 to EL3 causing immediate preemption of TSP. The EL3 is responsible 904 for saving and restoring the TSP context in this routing model. The 905 default routing model (when the value is 0) is to route non-secure 906 interrupts to TSP allowing it to save its context and hand over 907 synchronously to EL3 via an SMC. 908 909 .. note:: 910 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 911 must also be set to ``1``. 912 913- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 914 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 915 this delay. It can take values in the range (0-15). Default value is ``0`` 916 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 917 Platforms need to explicitly update this value based on their requirements. 918 919- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 920 linker. When the ``LINKER`` build variable points to the armlink linker, 921 this flag is enabled automatically. To enable support for armlink, platforms 922 will have to provide a scatter file for the BL image. Currently, Tegra 923 platforms use the armlink support to compile BL3-1 images. 924 925- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 926 memory region in the BL memory map or not (see "Use of Coherent memory in 927 TF-A" section in :ref:`Firmware Design`). It can take the value 1 928 (Coherent memory region is included) or 0 (Coherent memory region is 929 excluded). Default is 1. 930 931- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 932 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 933 Default is 0. 934 935- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 936 firmware configuration framework. This will move the io_policies into a 937 configuration device tree, instead of static structure in the code base. 938 939- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 940 at runtime using fconf. If this flag is enabled, COT descriptors are 941 statically captured in tb_fw_config file in the form of device tree nodes 942 and properties. Currently, COT descriptors used by BL2 are moved to the 943 device tree and COT descriptors used by BL1 are retained in the code 944 base statically. 945 946- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 947 runtime using firmware configuration framework. The platform specific SDEI 948 shared and private events configuration is retrieved from device tree rather 949 than static C structures at compile time. This is only supported if 950 SDEI_SUPPORT build flag is enabled. 951 952- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 953 and Group1 secure interrupts using the firmware configuration framework. The 954 platform specific secure interrupt property descriptor is retrieved from 955 device tree in runtime rather than depending on static C structure at compile 956 time. 957 958- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 959 This feature creates a library of functions to be placed in ROM and thus 960 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 961 is 0. 962 963- ``V``: Verbose build. If assigned anything other than 0, the build commands 964 are printed. Default is 0. 965 966- ``VERSION_STRING``: String used in the log output for each TF-A image. 967 Defaults to a string formed by concatenating the version number, build type 968 and build string. 969 970- ``W``: Warning level. Some compiler warning options of interest have been 971 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 972 each level enabling more warning options. Default is 0. 973 974 This option is closely related to the ``E`` option, which enables 975 ``-Werror``. 976 977 - ``W=0`` (default) 978 979 Enables a wide assortment of warnings, most notably ``-Wall`` and 980 ``-Wextra``, as well as various bad practices and things that are likely to 981 result in errors. Includes some compiler specific flags. No warnings are 982 expected at this level for any build. 983 984 - ``W=1`` 985 986 Enables warnings we want the generic build to include but are too time 987 consuming to fix at the moment. It re-enables warnings taken out for 988 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 989 to eventually be merged into ``W=0``. Some warnings are expected on some 990 builds, but new contributions should not introduce new ones. 991 992 - ``W=2`` (recommended) 993 994 Enables warnings we want the generic build to include but cannot be enabled 995 due to external libraries. This level is expected to eventually be merged 996 into ``W=0``. Lots of warnings are expected, primarily from external 997 libraries like zlib and compiler-rt, but new controbutions should not 998 introduce new ones. 999 1000 - ``W=3`` 1001 1002 Enables warnings that are informative but not necessary and generally too 1003 verbose and frequently ignored. A very large number of warnings are 1004 expected. 1005 1006 The exact set of warning flags depends on the compiler and TF-A warning 1007 level, however they are all succinctly set in the top-level Makefile. Please 1008 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1009 individual flags. 1010 1011- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1012 the CPU after warm boot. This is applicable for platforms which do not 1013 require interconnect programming to enable cache coherency (eg: single 1014 cluster platforms). If this option is enabled, then warm boot path 1015 enables D-caches immediately after enabling MMU. This option defaults to 0. 1016 1017- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1018 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1019 default value of this flag is ``no``. Note this option must be enabled only 1020 for ARM architecture greater than Armv8.5-A. 1021 1022- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1023 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1024 The default value of this flag is ``0``. 1025 1026 ``AT`` speculative errata workaround disables stage1 page table walk for 1027 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1028 produces either the correct result or failure without TLB allocation. 1029 1030 This boolean option enables errata for all below CPUs. 1031 1032 +---------+--------------+-------------------------+ 1033 | Errata | CPU | Workaround Define | 1034 +=========+==============+=========================+ 1035 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1036 +---------+--------------+-------------------------+ 1037 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1038 +---------+--------------+-------------------------+ 1039 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1040 +---------+--------------+-------------------------+ 1041 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1042 +---------+--------------+-------------------------+ 1043 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1044 +---------+--------------+-------------------------+ 1045 1046 .. note:: 1047 This option is enabled by build only if platform sets any of above defines 1048 mentioned in ’Workaround Define' column in the table. 1049 If this option is enabled for the EL3 software then EL2 software also must 1050 implement this workaround due to the behaviour of the errata mentioned 1051 in new SDEN document which will get published soon. 1052 1053- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1054 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1055 This flag is disabled by default. 1056 1057- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1058 host machine where a custom installation of OpenSSL is located, which is used 1059 to build the certificate generation, firmware encryption and FIP tools. If 1060 this option is not set, the default OS installation will be used. 1061 1062- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1063 functions that wait for an arbitrary time length (udelay and mdelay). The 1064 default value is 0. 1065 1066- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1067 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1068 optional architectural feature for AArch64. This flag can take the values 1069 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1070 and it is automatically disabled when the target architecture is AArch32. 1071 1072- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1073 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1074 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1075 feature for AArch64. This flag can take the values 0 to 2, to align with the 1076 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1077 disabled when the target architecture is AArch32. 1078 1079- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1080 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1081 but unused). This feature is available if trace unit such as ETMv4.x, and 1082 ETE(extending ETM feature) is implemented. This flag can take the values 1083 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1084 1085- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1086 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1087 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1088 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1089 1090- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1091 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1092 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1093 The default value is 0. 1094 1095- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1096 ``plat_can_cmo`` which will return zero if cache management operations should 1097 be skipped and non-zero otherwise. By default, this option is disabled which 1098 means platform hook won't be checked and CMOs will always be performed when 1099 related functions are called. 1100 1101GICv3 driver options 1102-------------------- 1103 1104GICv3 driver files are included using directive: 1105 1106``include drivers/arm/gic/v3/gicv3.mk`` 1107 1108The driver can be configured with the following options set in the platform 1109makefile: 1110 1111- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1112 Enabling this option will add runtime detection support for the 1113 GIC-600, so is safe to select even for a GIC500 implementation. 1114 This option defaults to 0. 1115 1116- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1117 for GIC-600 AE. Enabling this option will introduce support to initialize 1118 the FMU. Platforms should call the init function during boot to enable the 1119 FMU and its safety mechanisms. This option defaults to 0. 1120 1121- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1122 functionality. This option defaults to 0 1123 1124- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1125 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1126 functions. This is required for FVP platform which need to simulate GIC save 1127 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1128 1129- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1130 This option defaults to 0. 1131 1132- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1133 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1134 1135Debugging options 1136----------------- 1137 1138To compile a debug version and make the build more verbose use 1139 1140.. code:: shell 1141 1142 make PLAT=<platform> DEBUG=1 V=1 all 1143 1144AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1145(for example Arm-DS) might not support this and may need an older version of 1146DWARF symbols to be emitted by GCC. This can be achieved by using the 1147``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1148the version to 4 is recommended for Arm-DS. 1149 1150When debugging logic problems it might also be useful to disable all compiler 1151optimizations by using ``-O0``. 1152 1153.. warning:: 1154 Using ``-O0`` could cause output images to be larger and base addresses 1155 might need to be recalculated (see the **Memory layout on Arm development 1156 platforms** section in the :ref:`Firmware Design`). 1157 1158Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1159``LDFLAGS``: 1160 1161.. code:: shell 1162 1163 CFLAGS='-O0 -gdwarf-2' \ 1164 make PLAT=<platform> DEBUG=1 V=1 all 1165 1166Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1167ignored as the linker is called directly. 1168 1169It is also possible to introduce an infinite loop to help in debugging the 1170post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1171``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1172section. In this case, the developer may take control of the target using a 1173debugger when indicated by the console output. When using Arm-DS, the following 1174commands can be used: 1175 1176:: 1177 1178 # Stop target execution 1179 interrupt 1180 1181 # 1182 # Prepare your debugging environment, e.g. set breakpoints 1183 # 1184 1185 # Jump over the debug loop 1186 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1187 1188 # Resume execution 1189 continue 1190 1191Firmware update options 1192----------------------- 1193 1194- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1195 in defining the firmware update metadata structure. This flag is by default 1196 set to '2'. 1197 1198- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1199 firmware bank. Each firmware bank must have the same number of images as per 1200 the `PSA FW update specification`_. 1201 This flag is used in defining the firmware update metadata structure. This 1202 flag is by default set to '1'. 1203 1204- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1205 `PSA FW update specification`_. The default value is 0, and this is an 1206 experimental feature. 1207 PSA firmware update implementation has some limitations, such as BL2 is 1208 not part of the protocol-updatable images, if BL2 needs to be updated, then 1209 it should be done through another platform-defined mechanism, and it assumes 1210 that the platform's hardware supports CRC32 instructions. 1211 1212-------------- 1213 1214*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1215 1216.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1217.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1218.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1219.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1220.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1221