1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52 ENABLE_FEAT_GCS := 2 53ifeq (${ARCH},aarch64) 54ifeq (${SPM_MM}, 0) 55ifeq (${ENABLE_RME}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58endif 59endif 60endif 61endif 62endif 63 64# enable unconditionally for all builds 65ifeq (${ARCH}, aarch64) 66ifeq (${ENABLE_RME},0) 67 ENABLE_BRBE_FOR_NS := 2 68endif 69endif 70ENABLE_TRBE_FOR_NS := 2 71ENABLE_SYS_REG_TRACE_FOR_NS := 2 72ENABLE_FEAT_CSV2_2 := 2 73ENABLE_FEAT_PAN := 2 74ENABLE_FEAT_VHE := 2 75CTX_INCLUDE_NEVE_REGS := 2 76ENABLE_FEAT_SEL2 := 2 77ENABLE_TRF_FOR_NS := 2 78ENABLE_FEAT_ECV := 2 79ENABLE_FEAT_FGT := 2 80ENABLE_FEAT_TCR2 := 2 81ENABLE_FEAT_S2PIE := 2 82ENABLE_FEAT_S1PIE := 2 83ENABLE_FEAT_S2POE := 2 84ENABLE_FEAT_S1POE := 2 85endif 86 87# The FVP platform depends on this macro to build with correct GIC driver. 88$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 89 90# Pass FVP_CLUSTER_COUNT to the build system. 91$(eval $(call add_define,FVP_CLUSTER_COUNT)) 92 93# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 94$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 95 96# Pass FVP_MAX_PE_PER_CPU to the build system. 97$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 98 99# Pass FVP_GICR_REGION_PROTECTION to the build system. 100$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 101 102# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 103# choose the CCI driver , else the CCN driver 104ifeq ($(FVP_CLUSTER_COUNT), 0) 105$(error "Incorrect cluster count specified for FVP port") 106else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 107FVP_INTERCONNECT_DRIVER := FVP_CCI 108else 109FVP_INTERCONNECT_DRIVER := FVP_CCN 110endif 111 112$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 113 114# Choose the GIC sources depending upon the how the FVP will be invoked 115ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 116 117# The GIC model (GIC-600 or GIC-500) will be detected at runtime 118GICV3_SUPPORT_GIC600 := 1 119GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 120 121# Include GICv3 driver files 122include drivers/arm/gic/v3/gicv3.mk 123 124FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 125 plat/common/plat_gicv3.c \ 126 plat/arm/common/arm_gicv3.c 127 128 ifeq ($(filter 1,${RESET_TO_BL2} \ 129 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 130 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 131 endif 132 133else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 134 135# No GICv4 extension 136GIC_ENABLE_V4_EXTN := 0 137$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 138 139# Include GICv2 driver files 140include drivers/arm/gic/v2/gicv2.mk 141 142FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 143 plat/common/plat_gicv2.c \ 144 plat/arm/common/arm_gicv2.c 145 146FVP_DT_PREFIX := fvp-base-gicv2-psci 147else 148$(error "Incorrect GIC driver chosen on FVP port") 149endif 150 151ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 152FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 153else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 154FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 155 plat/arm/common/arm_ccn.c 156else 157$(error "Incorrect CCN driver chosen on FVP port") 158endif 159 160FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 161 plat/arm/board/fvp/fvp_security.c \ 162 plat/arm/common/arm_tzc400.c 163 164 165PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 166 -Iinclude/lib/psa 167 168 169PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 170 171FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 172 173ifeq (${ARCH}, aarch64) 174 175# select a different set of CPU files, depending on whether we compile for 176# hardware assisted coherency cores or not 177ifeq (${HW_ASSISTED_COHERENCY}, 0) 178# Cores used without DSU 179 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 180 lib/cpus/aarch64/cortex_a53.S \ 181 lib/cpus/aarch64/cortex_a57.S \ 182 lib/cpus/aarch64/cortex_a72.S \ 183 lib/cpus/aarch64/cortex_a73.S 184else 185# Cores used with DSU only 186 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 187 # AArch64-only cores 188 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ 189 lib/cpus/aarch64/cortex_a76ae.S \ 190 lib/cpus/aarch64/cortex_a77.S \ 191 lib/cpus/aarch64/cortex_a78.S \ 192 lib/cpus/aarch64/neoverse_n_common.S \ 193 lib/cpus/aarch64/neoverse_n1.S \ 194 lib/cpus/aarch64/neoverse_n2.S \ 195 lib/cpus/aarch64/neoverse_e1.S \ 196 lib/cpus/aarch64/neoverse_v1.S \ 197 lib/cpus/aarch64/neoverse_v2.S \ 198 lib/cpus/aarch64/cortex_a78_ae.S \ 199 lib/cpus/aarch64/cortex_a510.S \ 200 lib/cpus/aarch64/cortex_a710.S \ 201 lib/cpus/aarch64/cortex_a715.S \ 202 lib/cpus/aarch64/cortex_x3.S \ 203 lib/cpus/aarch64/cortex_a65.S \ 204 lib/cpus/aarch64/cortex_a65ae.S \ 205 lib/cpus/aarch64/cortex_a78c.S \ 206 lib/cpus/aarch64/cortex_hayes.S \ 207 lib/cpus/aarch64/cortex_hunter.S \ 208 lib/cpus/aarch64/cortex_hunter_elp_arm.S \ 209 lib/cpus/aarch64/cortex_x2.S \ 210 lib/cpus/aarch64/neoverse_poseidon.S \ 211 lib/cpus/aarch64/cortex_chaberton.S \ 212 lib/cpus/aarch64/cortex_blackhawk.S 213 endif 214 # AArch64/AArch32 cores 215 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 216 lib/cpus/aarch64/cortex_a75.S 217endif 218 219else 220FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 221 lib/cpus/aarch32/cortex_a57.S 222endif 223 224BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 225 drivers/arm/sp805/sp805.c \ 226 drivers/delay_timer/delay_timer.c \ 227 drivers/io/io_semihosting.c \ 228 lib/semihosting/semihosting.c \ 229 lib/semihosting/${ARCH}/semihosting_call.S \ 230 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 231 plat/arm/board/fvp/fvp_bl1_setup.c \ 232 plat/arm/board/fvp/fvp_err.c \ 233 plat/arm/board/fvp/fvp_io_storage.c \ 234 ${FVP_CPU_LIBS} \ 235 ${FVP_INTERCONNECT_SOURCES} 236 237ifeq (${USE_SP804_TIMER},1) 238BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 239else 240BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 241endif 242 243 244BL2_SOURCES += drivers/arm/sp805/sp805.c \ 245 drivers/io/io_semihosting.c \ 246 lib/utils/mem_region.c \ 247 lib/semihosting/semihosting.c \ 248 lib/semihosting/${ARCH}/semihosting_call.S \ 249 plat/arm/board/fvp/fvp_bl2_setup.c \ 250 plat/arm/board/fvp/fvp_err.c \ 251 plat/arm/board/fvp/fvp_io_storage.c \ 252 plat/arm/common/arm_nor_psci_mem_protect.c \ 253 ${FVP_SECURITY_SOURCES} 254 255 256ifeq (${COT_DESC_IN_DTB},1) 257BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 258endif 259 260ifeq (${ENABLE_RME},1) 261BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 262 263BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 264 plat/arm/board/fvp/fvp_realm_attest_key.c 265 266# FVP platform does not support RSS, but it can leverage RSS APIs to 267# provide hardcoded token/key on request. 268BL31_SOURCES += lib/psa/delegated_attestation.c 269 270endif 271 272ifeq (${ENABLE_FEAT_RNG_TRAP},1) 273BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 274endif 275 276ifeq (${RESET_TO_BL2},1) 277BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 278 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 279 ${FVP_CPU_LIBS} \ 280 ${FVP_INTERCONNECT_SOURCES} 281endif 282 283ifeq (${USE_SP804_TIMER},1) 284BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 285endif 286 287BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 288 ${FVP_SECURITY_SOURCES} 289 290ifeq (${USE_SP804_TIMER},1) 291BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 292endif 293 294BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 295 drivers/arm/smmu/smmu_v3.c \ 296 drivers/delay_timer/delay_timer.c \ 297 drivers/cfi/v2m/v2m_flash.c \ 298 lib/utils/mem_region.c \ 299 plat/arm/board/fvp/fvp_bl31_setup.c \ 300 plat/arm/board/fvp/fvp_console.c \ 301 plat/arm/board/fvp/fvp_pm.c \ 302 plat/arm/board/fvp/fvp_topology.c \ 303 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 304 plat/arm/common/arm_nor_psci_mem_protect.c \ 305 ${FVP_CPU_LIBS} \ 306 ${FVP_GIC_SOURCES} \ 307 ${FVP_INTERCONNECT_SOURCES} \ 308 ${FVP_SECURITY_SOURCES} 309 310# Support for fconf in BL31 311# Added separately from the above list for better readability 312ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 313BL31_SOURCES += lib/fconf/fconf.c \ 314 lib/fconf/fconf_dyn_cfg_getter.c \ 315 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 316 317BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 318 319ifeq (${SEC_INT_DESC_IN_FCONF},1) 320BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 321endif 322 323endif 324 325ifeq (${USE_SP804_TIMER},1) 326BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 327else 328BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 329endif 330 331# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 332ifdef UNIX_MK 333FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 334FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 335 ${PLAT}_fw_config.dts \ 336 ${PLAT}_tb_fw_config.dts \ 337 ${PLAT}_soc_fw_config.dts \ 338 ${PLAT}_nt_fw_config.dts \ 339 ) 340 341FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 342FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 343FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 344FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 345 346ifeq (${SPD},tspd) 347FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 348FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 349 350# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 351$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 352endif 353 354ifeq (${SPD},spmd) 355 356ifeq ($(ARM_SPMC_MANIFEST_DTS),) 357ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 358endif 359 360FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 361FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 362 363# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 364$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 365endif 366 367# Add the FW_CONFIG to FIP and specify the same to certtool 368$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 369# Add the TB_FW_CONFIG to FIP and specify the same to certtool 370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 371# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 373# Add the NT_FW_CONFIG to FIP and specify the same to certtool 374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 375 376FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 377$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 378 379# Add the HW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 381endif 382 383# Enable dynamic mitigation support by default 384DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 385 386ifneq (${ENABLE_FEAT_AMU},0) 387BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 388 lib/cpus/aarch64/cpuamu_helpers.S 389 390ifeq (${HW_ASSISTED_COHERENCY}, 1) 391BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 392 lib/cpus/aarch64/neoverse_n1_pubsub.c 393endif 394endif 395 396ifeq (${RAS_EXTENSION},1) 397BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 398endif 399 400ifneq (${ENABLE_STACK_PROTECTOR},0) 401PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 402endif 403 404ifeq (${ARCH},aarch32) 405 NEED_BL32 := yes 406endif 407 408# Enable the dynamic translation tables library. 409ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 410 ifeq (${ARCH},aarch32) 411 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 412 else # AArch64 413 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 414 endif 415endif 416 417ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 418 ifeq (${ARCH},aarch32) 419 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 420 else # AArch64 421 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 422 ifeq (${SPD},tspd) 423 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 424 endif 425 endif 426endif 427 428ifeq (${USE_DEBUGFS},1) 429 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 430endif 431 432# Add support for platform supplied linker script for BL31 build 433$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 434 435ifneq (${RESET_TO_BL2}, 0) 436 override BL1_SOURCES = 437endif 438 439# RSS is not supported on FVP right now. Thus, we use the mocked version 440# of the provided PSA APIs. They return with success and hard-coded token/key. 441PLAT_RSS_NOT_SUPPORTED := 1 442 443# Include Measured Boot makefile before any Crypto library makefile. 444# Crypto library makefile may need default definitions of Measured Boot build 445# flags present in Measured Boot makefile. 446ifeq (${MEASURED_BOOT},1) 447 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 448 $(info Including ${RSS_MEASURED_BOOT_MK}) 449 include ${RSS_MEASURED_BOOT_MK} 450 451 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 452 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 453 endif 454 455 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 456 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 457endif 458 459include plat/arm/board/common/board_common.mk 460include plat/arm/common/arm_common.mk 461 462ifeq (${MEASURED_BOOT},1) 463BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 464 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 465 lib/psa/measured_boot.c 466 467BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 468 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 469 lib/psa/measured_boot.c 470 471# Even though RSS is not supported on FVP (see above), we support overriding 472# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 473# the code to detect any build regressions. The resulting firmware will not be 474# functional. 475ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 476 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 477 include drivers/arm/rss/rss_comms.mk 478 BL1_SOURCES += ${RSS_COMMS_SOURCES} 479 BL2_SOURCES += ${RSS_COMMS_SOURCES} 480 BL31_SOURCES += ${RSS_COMMS_SOURCES} 481 482 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 483 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 484 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 485endif 486 487endif 488 489ifeq (${DRTM_SUPPORT}, 1) 490BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 491 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 492 plat/arm/board/fvp/fvp_drtm_err.c \ 493 plat/arm/board/fvp/fvp_drtm_measurement.c \ 494 plat/arm/board/fvp/fvp_drtm_stub.c \ 495 plat/arm/common/arm_dyn_cfg.c \ 496 plat/arm/board/fvp/fvp_err.c 497endif 498 499ifeq (${TRUSTED_BOARD_BOOT}, 1) 500BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 501BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 502 503# FVP being a development platform, enable capability to disable Authentication 504# dynamically if TRUSTED_BOARD_BOOT is set. 505DYN_DISABLE_AUTH := 1 506endif 507 508ifeq (${SPMC_AT_EL3}, 1) 509PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 510endif 511 512PSCI_OS_INIT_MODE := 1 513