feat(cpus): add support for arcadia cpu

Add basic CPU library code to support the Arcadia CPU.

Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43
Signed-off-by: Govindraj Raja <govindraj.raja@arm

feat(cpus): add support for arcadia cpu

Add basic CPU library code to support the Arcadia CPU.

Change-Id: Iecb0634dc6dcb34e9b5fda4902335530d237cc43
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge "feat(sctlr2): add support for FEAT_SCTLR2" into integration

Merge "feat(the): add support for FEAT_THE" into integration

feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable

feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable for a platform. This patch also supports the new
RMM_EL3_FEATURES interface, that RMM can use to query for support for
HES based signing. The new interface exposes a feature register with
different bits defining different discoverable features. This new
interface is available starting the 0.4 version of the RMM-EL3
interface, causing the version to bump up. This patch also adds a
platform port for FVP that implements the platform hooks required to
enable the new SMCs, but it does not push to a HES and instead copies a
zeroed buffer in EL3.

Change-Id: I69c110252835122a9533e71bdcce10b5f2a686b2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

show more ...

feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the

feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switchin

feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up

feat(handoff): make tl generation flexible

Make the process of compiling a TL from DT source flexible. Provide a
top level recipe to make it easier for developers to build a transfer
list. Clean up integration of TLC into the build system.

Change-Id: I4466e27a457dfd5bf709dc3a360a2b63bf6030ce
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

Merge "feat(fvp): scale SP_MIN max size based on SRAM size" into integration

Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform tok

Merge changes from topic "draft-ffm-rats-cca-token-00" into integration

* changes:
refactor(docs): update RSE docs to match the example CCA token
refactor(qemu): use the example CCA platform token from iat-verifier
refactor(fvp): use the example CCA platform token from iat-verifier

show more ...

Merge "refactor(rmmd): plat token requests in pieces" into integration

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token

refactor(rmmd): plat token requests in pieces

Until now, the attestation token size was limited by the size of the
shared buffer between RMM and TF-A. With this change, RMM can now
request the token in pieces, so they fit in the shared buffer. A new
output parameter was added to the SMC call, which will return (along
with the size of bytes copied into the buffer) the number of bytes
of the token that remain to be retrieved.

TF-A will keep an offset variable that will indicate the position in
the token where the next call will retrieve bytes from. This offset
will be increased on every call by adding the number number of bytes
copied. If the received hash size is not 0, TF-A will reset the
offset to 0 and copy from that position on.

The SMC call will now return at most the size of the shared buffer
in bytes on every call. Therefore, from now on, multiple SMC calls
may be needed to be issued if the token size exceeds the shared
buffer size.

Change-Id: I591f7013d06f64e98afaf9535dbea6f815799723
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

show more ...

refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cc

refactor(fvp): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in the FVP platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia23f0dffe618dca04f9f3c46c953a6f021101b09

show more ...

fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values,

fix(fvp): enable FEAT_MTE2

ENABLE_FEAT_MTE2 controls the trapping of some MTE related system
registers. If the memory_tagging_support_level parameter on the FVP
command line is set to higher values, non-secure world will see the
feature bits in the CPU ID registers and will use those registers,
triggering a panic in BL31.

Enable the feature in the optional form for the FVP build, to avoid any
panics.

Change-Id: I26ba444d784adf165db81048f93e11361c7f11ac
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to

feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to
the SRAM size used to build the FVP platform.

Change-Id: I95527e8ae6f8a73c336ed4fe05ace5de86d8991d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): ad

Merge changes from topic "mp/simd_ctxt_mgmt" into integration

* changes:
feat(fvp): allow SIMD context to be put in TZC DRAM
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
feat(fvp): add Cactus partition manifest for EL3 SPMC
chore(simd): remove unused macros and utilities for FP
feat(el3-spmc): support simd context management upon world switch
feat(trusty): switch to simd_ctx_save/restore apis
feat(pncd): switch to simd_ctx_save/restore apis
feat(spm-mm): switch to simd_ctx_save/restore APIs
feat(simd): add rules to rationalize simd ctxt mgmt
feat(simd): introduce simd context helper APIs
feat(simd): add routines to save, restore sve state
feat(simd): add sve state to simd ctxt struct
feat(simd): add data struct for simd ctxt management

show more ...

feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are all

feat(fvp): allow SIMD context to be put in TZC DRAM

This patch demonstrates the capability of SEPARATE_SIMD_SECTION build
flag through which the memory intensive SIMD context data structures
are allocated in a separate section withtin the TZC DRAM space.

Change-Id: Idf3f232a7960a8f84f279d496c76953a6dad2009
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad7

feat(fvp): add Cactus partition manifest for EL3 SPMC

This patch adds the SP partition manifest to boot Cactus SP on
EL3 SPMC to be used with FVP platform.

Change-Id: I88b36f6ac21ebba7fa93aef75dad74bb9ee5c944
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778

feat(simd): add rules to rationalize simd ctxt mgmt

Illegal combinations of build flags associated with SIMD context
management are flagged by the build system.

Change-Id: I3192af3889e1e864c7875778616e167ba6894195
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

Merge changes from topic "romlib-fixes" into integration

* changes:
fix(romlib): wrap indirectly included functions
fix(arm): remove duplicate jumptable entry

Merge changes from topic "cot-dt2c" into integration

* changes:
feat(arm): update documentation for cot-dt2c
feat(arm): remove the bl2 static c file
feat(arm): generate tbbr c file CoT dt2c

Merge changes from topic "cot-dt2c" into integration

* changes:
feat(arm): update documentation for cot-dt2c
feat(arm): remove the bl2 static c file
feat(arm): generate tbbr c file CoT dt2c
feat(arm): makefile invoke CoT dt2c
feat(auth): standalone CoT dt2c tool
refactor(auth): separate bl1 and bl2 CoT
refactor(st): align the NV counter naming
refactor(fvp): align the NV counter naming

show more ...

Merge "feat(spm): change UART0-1 to NS device region" into integration

refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renamin

refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.

Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

show more ...

fix(arm): remove duplicate jumptable entry

Change-Id: I4cc4ef493318372ec0d0531ca3e98196e7065ab9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

feat(arm): add fw handoff support for RESET_TO_BL31

Change-Id: I78f3c5606f0221bb5fc613a973a7d3fe187db35b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge "fix(fvp): add secure uart interrupt in device region" into integration