| 0dd41951 | 21-Jun-2017 |
David Cunado <david.cunado@arm.com> |
Resolve signed-unsigned comparison issues
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / e
Resolve signed-unsigned comparison issues
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / errors in the TF static analysis.
This patch addresses these issues by migrating impacted variables from
signed ints to unsigned ints and vice verse where applicable.
Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53
Signed-off-by: David Cunado <david.cunado@arm.com>
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| ccf39111 | 26-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #994 from soby-mathew/sm/fwu_fix
Fix FWU and cache helper optimization |
| 73e11b43 | 23-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #976 from etienne-lms/minor-psci
psci: minor fixes in lib |
| 9151ac0e | 23-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #997 from dp-arm/dp/spe
aarch64: Enable Statistical Profiling Extensions for lower ELs |
| ee881c15 | 23-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #995 from davidcunado-arm/dc/init_reg
Fully initialise essential control registers |
| aa8d5f88 | 07-Jun-2017 |
Etienne Carriere <etienne.carriere@st.com> |
PSCI: use same function prototype as in header file
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> |
| c283e05a | 22-Jun-2017 |
Etienne Carriere <etienne.carriere@st.com> |
psci: minor fixes in lib
Call svc_suspend_finish if registered.
psci_get_stat() is static to psci_stat.c
Fix types used in comparison.
Fix coding style (empty line between variable definition and in
psci: minor fixes in lib
Call svc_suspend_finish if registered.
psci_get_stat() is static to psci_stat.c
Fix types used in comparison.
Fix coding style (empty line between variable definition and instructions
block).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| a94cc374 | 19-Jun-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
Apply workarounds for A53 Cat A Errata 835769 and 843419
These errata are only applicable to AArch64 state. See the errata notice
for more details:
http://infocenter.arm.com/help/index.jsp?topic=/co
Apply workarounds for A53 Cat A Errata 835769 and 843419
These errata are only applicable to AArch64 state. See the errata notice
for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html
Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419.
Enable both of them for Juno.
Apply the 835769 workaround as following:
* Compile with -mfix-cortex-a53-835769
* Link with --fix-cortex-a53-835769
Apply the 843419 workaround as following:
* Link with --fix-cortex-a53-843419
The erratum 843419 workaround can lead the linker to create new sections
suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the
linker to create new "*.stub" sections with no particular alignment.
Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for
architecture-specific linker options.
Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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| 6f512a3d | 20-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execu
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under
specific circumstances in Cortex-A57 r0p0. The workaround is to
execute DSB and TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.
The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.
NOTE: This workaround is present in AArch64 TF and already enabled by
default on Juno.
Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| d832aee9 | 23-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, befo
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained. This is to
avoid a potential invalid memory access in SEL1.
SPE is architecturally specified only for AArch64.
Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| 18f2efd6 | 13-Apr-2017 |
David Cunado <david.cunado@arm.com> |
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the res
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
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| 3ec5204c | 15-Jun-2017 |
Soby Mathew <soby.mathew@arm.com> |
Exit early if size zero for cache helpers
This patch enables cache helper functions `flush_dcache_range`,
`clean_dcache_range` and `invalidate_dcache_range` to exit early
if the size argument specif
Exit early if size zero for cache helpers
This patch enables cache helper functions `flush_dcache_range`,
`clean_dcache_range` and `invalidate_dcache_range` to exit early
if the size argument specified is zero
Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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|
| e036660a | 20-Jun-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #983 from dp-arm/dp/aarch32-errata
aarch32: Implement errata workarounds for Cortex A53 and A57 |
| 94f7d1e2 | 05-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Implement errata workarounds for Cortex A57
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064
Sig
aarch32: Implement errata workarounds for Cortex A57
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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|
| 3749d853 | 05-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Sig
aarch32: Implement errata workarounds for Cortex A53
This brings the implementation on par with the software
errata workarounds for AArch64.
Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| 56e04999 | 05-Jun-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
aarch32: Implement cpu_rev_var_hs()
Helper function to assist with errata workaround application.
Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e
Signed-off-by: Dimitris Papastamos <dimitris.p
aarch32: Implement cpu_rev_var_hs()
Helper function to assist with errata workaround application.
Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| 2676f6a9 | 16-Jun-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
xlat_tables_v2: fix signed/unsigned comparisons
This patch changes input param level in xlat_tables_print_internal() to
an unsigned int to fix the signed/unsigned comparison warnings. The
compiler c
xlat_tables_v2: fix signed/unsigned comparisons
This patch changes input param level in xlat_tables_print_internal() to
an unsigned int to fix the signed/unsigned comparison warnings. The
compiler complains about these warnings, thus halting the build flow
for Tegra platforms.
Change-Id: Ieccc262a63daca7a26ca6a14d81466397af8b89f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: David Cunado <david.cunado@arm.com>
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| fb7d32e5 | 05-Jun-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDA
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 6311f63d | 07-Jun-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: enable 'signed-comparison' compilation warning/errors
This patch enables the 'sign-compare' flag, to enable warning/errors
for comparisons between signed/unsigned variables. The warning has
b
Tegra: enable 'signed-comparison' compilation warning/errors
This patch enables the 'sign-compare' flag, to enable warning/errors
for comparisons between signed/unsigned variables. The warning has
been enabled for all the Tegra platforms, to start with.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d40ab484 | 09-Nov-2016 |
David Wang <david.wang@arm.com> |
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardwa
Add support for Cortex-A75 and Cortex-A55 CPUs
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit
(DSU). The power-down and power-up sequences are therefore mostly
managed in hardware, and required software operations are considerably
simpler.
Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 4df22469 | 24-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
compiler-rt: Remove unused int_util.[ch] files
Change-Id: I32fc523e3178b7e50191682241904d52499ff708
Signed-off-by: dp-arm <dimitris.papastamos@arm.com> |
| 22fa58cb | 05-May-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Use a callee-saved register to be AAPCS-compliant
x8 is not a callee-saved register and can be corrupted.
Use x19 instead to be AAPCS-compliant.
Fixes ARM-software/tf-issues#478
Change-Id: Ib4f114
Use a callee-saved register to be AAPCS-compliant
x8 is not a callee-saved register and can be corrupted.
Use x19 instead to be AAPCS-compliant.
Fixes ARM-software/tf-issues#478
Change-Id: Ib4f114c36f4c11351ae856f953c45dca92b27c3b
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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| 6cfba92c | 22-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #945 from antonio-nino-diaz-arm/an/xlat-dependency
xlat: Fix missing header file dependency |
| 81602a97 | 22-May-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #939 from dp-arm/dp/AArch32_tbbr
Add TBBR and FWU support for AArch32 |
| b506f304 | 17-May-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
xlat: Fix missing header file dependency
xlat_tables_arch.h uses the platform macro `PLAT_VIRT_ADDR_SPACE_SIZE`.
This macro is defined in xlat_tables_private.h only if the platform
still uses the de
xlat: Fix missing header file dependency
xlat_tables_arch.h uses the platform macro `PLAT_VIRT_ADDR_SPACE_SIZE`.
This macro is defined in xlat_tables_private.h only if the platform
still uses the deprecated `ADDR_SPACE_SIZE`.
Change-Id: I1c3b12ebd96bdfe9bf94b26d440c03bc0f8c0b24
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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