1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <gicv2.h> 12 #include <hi6220.h> 13 #include <hisi_ipc.h> 14 #include <hisi_pwrc.h> 15 #include <hisi_sram_map.h> 16 #include <mmio.h> 17 #include <psci.h> 18 #include <sp804_delay_timer.h> 19 20 #include "hikey_def.h" 21 22 #define CORE_PWR_STATE(state) \ 23 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 24 #define CLUSTER_PWR_STATE(state) \ 25 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 26 #define SYSTEM_PWR_STATE(state) \ 27 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 28 29 static uintptr_t hikey_sec_entrypoint; 30 31 static int hikey_pwr_domain_on(u_register_t mpidr) 32 { 33 int cpu, cluster; 34 int curr_cluster; 35 36 cluster = MPIDR_AFFLVL1_VAL(mpidr); 37 cpu = MPIDR_AFFLVL0_VAL(mpidr); 38 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); 39 if (cluster != curr_cluster) 40 hisi_ipc_cluster_on(cpu, cluster); 41 42 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 43 hisi_ipc_cpu_on(cpu, cluster); 44 return 0; 45 } 46 47 static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) 48 { 49 unsigned long mpidr; 50 int cpu, cluster; 51 52 mpidr = read_mpidr(); 53 cluster = MPIDR_AFFLVL1_VAL(mpidr); 54 cpu = MPIDR_AFFLVL0_VAL(mpidr); 55 56 57 /* 58 * Enable CCI coherency for this cluster. 59 * No need for locks as no other cpu is active at the moment. 60 */ 61 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 62 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 63 64 /* Zero the jump address in the mailbox for this cpu */ 65 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 66 67 /* Program the GIC per-cpu distributor or re-distributor interface */ 68 gicv2_pcpu_distif_init(); 69 /* Enable the GIC cpu interface */ 70 gicv2_cpuif_enable(); 71 } 72 73 void hikey_pwr_domain_off(const psci_power_state_t *target_state) 74 { 75 unsigned long mpidr; 76 int cpu, cluster; 77 78 mpidr = read_mpidr(); 79 cluster = MPIDR_AFFLVL1_VAL(mpidr); 80 cpu = MPIDR_AFFLVL0_VAL(mpidr); 81 82 gicv2_cpuif_disable(); 83 hisi_ipc_cpu_off(cpu, cluster); 84 85 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 86 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 87 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 88 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 89 90 hisi_ipc_cluster_off(cpu, cluster); 91 } 92 } 93 94 static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state) 95 { 96 u_register_t mpidr = read_mpidr_el1(); 97 unsigned int cpu = mpidr & MPIDR_CPU_MASK; 98 unsigned int cluster = 99 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; 100 101 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 102 return; 103 104 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 105 106 /* Program the jump address for the target cpu */ 107 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 108 109 gicv2_cpuif_disable(); 110 111 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 112 hisi_ipc_cpu_suspend(cpu, cluster); 113 } 114 115 /* Perform the common cluster specific operations */ 116 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 117 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 118 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 119 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 120 121 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 122 hisi_pwrc_set_cluster_wfi(1); 123 hisi_pwrc_set_cluster_wfi(0); 124 hisi_ipc_psci_system_off(); 125 } else 126 hisi_ipc_cluster_suspend(cpu, cluster); 127 } 128 } 129 130 static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 131 { 132 unsigned long mpidr; 133 unsigned int cluster, cpu; 134 135 /* Nothing to be done on waking up from retention from CPU level */ 136 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 137 return; 138 139 /* Get the mpidr for this cpu */ 140 mpidr = read_mpidr_el1(); 141 cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT; 142 cpu = mpidr & MPIDR_CPU_MASK; 143 144 /* Enable CCI coherency for cluster */ 145 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 146 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 147 148 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 149 150 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 151 gicv2_distif_init(); 152 gicv2_pcpu_distif_init(); 153 gicv2_cpuif_enable(); 154 } else { 155 gicv2_pcpu_distif_init(); 156 gicv2_cpuif_enable(); 157 } 158 } 159 160 static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state) 161 { 162 int i; 163 164 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 165 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 166 } 167 168 static void __dead2 hikey_system_off(void) 169 { 170 NOTICE("%s: off system\n", __func__); 171 172 /* Pull down GPIO_0_0 to trigger PMIC shutdown */ 173 mmio_write_32(0xF8001810, 0x2); /* Pinmux */ 174 mmio_write_8(0xF8011400, 1); /* Pin direction */ 175 mmio_write_8(0xF8011004, 0); /* Pin output value */ 176 177 /* Wait for 2s to power off system by PMIC */ 178 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 179 mdelay(2000); 180 181 /* 182 * PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low, 183 * and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2 184 * through Jumper 1-2. So, to complete shutdown, user needs to manually 185 * remove Jumper 1-2. 186 */ 187 NOTICE("+------------------------------------------+\n"); 188 NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n"); 189 NOTICE("| DANGER: SoC is still burning. DANGER! |\n"); 190 NOTICE("| Board will be reboot to avoid overheat |\n"); 191 NOTICE("+------------------------------------------+\n"); 192 193 /* Send the system reset request */ 194 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 195 196 wfi(); 197 panic(); 198 } 199 200 static void __dead2 hikey_system_reset(void) 201 { 202 /* Send the system reset request */ 203 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 204 isb(); 205 dsb(); 206 207 wfi(); 208 panic(); 209 } 210 211 int hikey_validate_power_state(unsigned int power_state, 212 psci_power_state_t *req_state) 213 { 214 int pstate = psci_get_pstate_type(power_state); 215 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 216 int i; 217 218 assert(req_state); 219 220 if (pwr_lvl > PLAT_MAX_PWR_LVL) 221 return PSCI_E_INVALID_PARAMS; 222 223 /* Sanity check the requested state */ 224 if (pstate == PSTATE_TYPE_STANDBY) { 225 /* 226 * It's possible to enter standby only on power level 0 227 * Ignore any other power level. 228 */ 229 if (pwr_lvl != MPIDR_AFFLVL0) 230 return PSCI_E_INVALID_PARAMS; 231 232 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 233 PLAT_MAX_RET_STATE; 234 } else { 235 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) 236 req_state->pwr_domain_state[i] = 237 PLAT_MAX_OFF_STATE; 238 } 239 240 /* 241 * We expect the 'state id' to be zero. 242 */ 243 if (psci_get_pstate_id(power_state)) 244 return PSCI_E_INVALID_PARAMS; 245 246 return PSCI_E_SUCCESS; 247 } 248 249 static int hikey_validate_ns_entrypoint(uintptr_t entrypoint) 250 { 251 /* 252 * Check if the non secure entrypoint lies within the non 253 * secure DRAM. 254 */ 255 if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) 256 return PSCI_E_SUCCESS; 257 258 return PSCI_E_INVALID_ADDRESS; 259 } 260 261 static const plat_psci_ops_t hikey_psci_ops = { 262 .cpu_standby = NULL, 263 .pwr_domain_on = hikey_pwr_domain_on, 264 .pwr_domain_on_finish = hikey_pwr_domain_on_finish, 265 .pwr_domain_off = hikey_pwr_domain_off, 266 .pwr_domain_suspend = hikey_pwr_domain_suspend, 267 .pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish, 268 .system_off = hikey_system_off, 269 .system_reset = hikey_system_reset, 270 .validate_power_state = hikey_validate_power_state, 271 .validate_ns_entrypoint = hikey_validate_ns_entrypoint, 272 .get_sys_suspend_power_state = hikey_get_sys_suspend_power_state, 273 }; 274 275 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 276 const plat_psci_ops_t **psci_ops) 277 { 278 hikey_sec_entrypoint = sec_entrypoint; 279 280 /* 281 * Initialize PSCI ops struct 282 */ 283 *psci_ops = &hikey_psci_ops; 284 return 0; 285 } 286