1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_PRIVATE_H__ 8 #define __GICV3_PRIVATE_H__ 9 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <mmio.h> 13 #include <stdint.h> 14 #include "../common/gic_common_private.h" 15 16 /******************************************************************************* 17 * GICv3 private macro definitions 18 ******************************************************************************/ 19 20 /* Constants to indicate the status of the RWP bit */ 21 #define RWP_TRUE 1 22 #define RWP_FALSE 0 23 24 /* 25 * Macro to wait for updates to : 26 * GICD_CTLR[2:0] - the Group Enables 27 * GICD_CTLR[5:4] - the ARE bits 28 * GICD_ICENABLERn - the clearing of enable state for SPIs 29 */ 30 #define gicd_wait_for_pending_write(gicd_base) \ 31 do { \ 32 ; \ 33 } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 34 35 /* 36 * Macro to convert an mpidr to a value suitable for programming into a 37 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 38 * to GICv3. 39 */ 40 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 41 ((mpidr & ~(0xff << 24)) | \ 42 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 43 44 /* 45 * Macro to wait for updates to : 46 * GICR_ICENABLER0 47 * GICR_CTLR.DPG1S 48 * GICR_CTLR.DPG1NS 49 * GICR_CTLR.DPG0 50 */ 51 #define gicr_wait_for_pending_write(gicr_base) \ 52 do { \ 53 ; \ 54 } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 55 56 /* 57 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 58 * are zeroes. 59 */ 60 #ifdef AARCH32 61 #define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff) 62 #else 63 #define mpidr_from_gicr_typer(typer_val) \ 64 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 65 (((typer_val) >> 32) & 0xffffff)) 66 #endif 67 68 /******************************************************************************* 69 * Private GICv3 function prototypes for accessing entire registers. 70 * Note: The raw register values correspond to multiple interrupt IDs and 71 * the number of interrupt IDs involved depends on the register accessed. 72 ******************************************************************************/ 73 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 74 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 75 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 76 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 77 78 /******************************************************************************* 79 * Private GICv3 function prototypes for accessing the GIC registers 80 * corresponding to a single interrupt ID. These functions use bitwise 81 * operations or appropriate register accesses to modify or return 82 * the bit-field corresponding the single interrupt ID. 83 ******************************************************************************/ 84 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 85 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 86 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 87 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 88 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 89 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 90 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 91 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 92 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 93 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 94 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 95 96 /******************************************************************************* 97 * Private GICv3 helper function prototypes 98 ******************************************************************************/ 99 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 100 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 101 void gicv3_secure_spis_configure(uintptr_t gicd_base, 102 unsigned int num_ints, 103 const unsigned int *sec_intr_list, 104 unsigned int int_grp); 105 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 106 unsigned int num_ints, 107 const unsigned int *sec_intr_list, 108 unsigned int int_grp); 109 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 110 unsigned int rdistif_num, 111 uintptr_t gicr_base, 112 mpidr_hash_fn mpidr_to_core_pos); 113 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 114 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 115 116 /******************************************************************************* 117 * GIC Distributor interface accessors 118 ******************************************************************************/ 119 static inline unsigned int gicd_read_pidr2(uintptr_t base) 120 { 121 return mmio_read_32(base + GICD_PIDR2_GICV3); 122 } 123 124 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 125 { 126 assert(id >= MIN_SPI_ID); 127 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 128 } 129 130 static inline void gicd_write_irouter(uintptr_t base, 131 unsigned int id, 132 unsigned long long affinity) 133 { 134 assert(id >= MIN_SPI_ID); 135 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 136 } 137 138 static inline void gicd_clr_ctlr(uintptr_t base, 139 unsigned int bitmap, 140 unsigned int rwp) 141 { 142 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 143 if (rwp) 144 gicd_wait_for_pending_write(base); 145 } 146 147 static inline void gicd_set_ctlr(uintptr_t base, 148 unsigned int bitmap, 149 unsigned int rwp) 150 { 151 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 152 if (rwp) 153 gicd_wait_for_pending_write(base); 154 } 155 156 /******************************************************************************* 157 * GIC Redistributor interface accessors 158 ******************************************************************************/ 159 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 160 { 161 return mmio_read_64(base + GICR_CTLR); 162 } 163 164 static inline unsigned long long gicr_read_typer(uintptr_t base) 165 { 166 return mmio_read_64(base + GICR_TYPER); 167 } 168 169 static inline unsigned int gicr_read_waker(uintptr_t base) 170 { 171 return mmio_read_32(base + GICR_WAKER); 172 } 173 174 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 175 { 176 mmio_write_32(base + GICR_WAKER, val); 177 } 178 179 /******************************************************************************* 180 * GIC Re-distributor functions for accessing entire registers. 181 * Note: The raw register values correspond to multiple interrupt IDs and 182 * the number of interrupt IDs involved depends on the register accessed. 183 ******************************************************************************/ 184 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 185 { 186 return mmio_read_32(base + GICR_ICENABLER0); 187 } 188 189 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 190 { 191 mmio_write_32(base + GICR_ICENABLER0, val); 192 } 193 194 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 195 { 196 return mmio_read_32(base + GICR_ISENABLER0); 197 } 198 199 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 200 { 201 mmio_write_32(base + GICR_ISENABLER0, val); 202 } 203 204 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 205 { 206 return mmio_read_32(base + GICR_IGROUPR0); 207 } 208 209 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 210 { 211 mmio_write_32(base + GICR_IGROUPR0, val); 212 } 213 214 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 215 { 216 return mmio_read_32(base + GICR_IGRPMODR0); 217 } 218 219 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 220 { 221 mmio_write_32(base + GICR_IGRPMODR0, val); 222 } 223 224 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 225 { 226 return mmio_read_32(base + GICR_ICFGR1); 227 } 228 229 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 230 { 231 mmio_write_32(base + GICR_ICFGR1, val); 232 } 233 234 #endif /* __GICV3_PRIVATE_H__ */ 235