1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <interrupt_mgmt.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <smcc_helpers.h> 17 #include <string.h> 18 #include <utils.h> 19 20 21 /******************************************************************************* 22 * Context management library initialisation routine. This library is used by 23 * runtime services to share pointers to 'cpu_context' structures for the secure 24 * and non-secure states. Management of the structures and their associated 25 * memory is not done by the context management library e.g. the PSCI service 26 * manages the cpu context used for entry from and exit to the non-secure state. 27 * The Secure payload dispatcher service manages the context(s) corresponding to 28 * the secure state. It also uses this library to get access to the non-secure 29 * state cpu context pointers. 30 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 31 * which will used for programming an entry into a lower EL. The same context 32 * will used to save state upon exception entry from that EL. 33 ******************************************************************************/ 34 void cm_init(void) 35 { 36 /* 37 * The context management library has only global data to intialize, but 38 * that will be done when the BSS is zeroed out 39 */ 40 } 41 42 /******************************************************************************* 43 * The following function initializes the cpu_context 'ctx' for 44 * first use, and sets the initial entrypoint state as specified by the 45 * entry_point_info structure. 46 * 47 * The security state to initialize is determined by the SECURE attribute 48 * of the entry_point_info. The function returns a pointer to the initialized 49 * context and sets this as the next context to return to. 50 * 51 * The EE and ST attributes are used to configure the endianess and secure 52 * timer availability for the new execution context. 53 * 54 * To prepare the register state for entry call cm_prepare_el3_exit() and 55 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 56 * cm_e1_sysreg_context_restore(). 57 ******************************************************************************/ 58 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 59 { 60 unsigned int security_state; 61 uint32_t scr_el3; 62 el3_state_t *state; 63 gp_regs_t *gp_regs; 64 unsigned long sctlr_elx; 65 66 assert(ctx); 67 68 security_state = GET_SECURITY_STATE(ep->h.attr); 69 70 /* Clear any residual register values from the context */ 71 zeromem(ctx, sizeof(*ctx)); 72 73 /* 74 * SCR_EL3 was initialised during reset sequence in macro 75 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 76 * affect the next EL. 77 * 78 * The following fields are initially set to zero and then updated to 79 * the required value depending on the state of the SPSR_EL3 and the 80 * Security state and entrypoint attributes of the next EL. 81 */ 82 scr_el3 = read_scr(); 83 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 84 SCR_ST_BIT | SCR_HCE_BIT); 85 /* 86 * SCR_NS: Set the security state of the next EL. 87 */ 88 if (security_state != SECURE) 89 scr_el3 |= SCR_NS_BIT; 90 /* 91 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 92 * Exception level as specified by SPSR. 93 */ 94 if (GET_RW(ep->spsr) == MODE_RW_64) 95 scr_el3 |= SCR_RW_BIT; 96 /* 97 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 98 * Secure timer registers to EL3, from AArch64 state only, if specified 99 * by the entrypoint attributes. 100 */ 101 if (EP_GET_ST(ep->h.attr)) 102 scr_el3 |= SCR_ST_BIT; 103 104 #ifndef HANDLE_EA_EL3_FIRST 105 /* 106 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 107 * to EL3 when executing at a lower EL. When executing at EL3, External 108 * Aborts are taken to EL3. 109 */ 110 scr_el3 &= ~SCR_EA_BIT; 111 #endif 112 113 #ifdef IMAGE_BL31 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(security_state); 119 #endif 120 121 /* 122 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 123 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 124 * next mode is Hyp. 125 */ 126 if ((GET_RW(ep->spsr) == MODE_RW_64 127 && GET_EL(ep->spsr) == MODE_EL2) 128 || (GET_RW(ep->spsr) != MODE_RW_64 129 && GET_M32(ep->spsr) == MODE32_hyp)) { 130 scr_el3 |= SCR_HCE_BIT; 131 } 132 133 /* 134 * Initialise SCTLR_EL1 to the reset value corresponding to the target 135 * execution state setting all fields rather than relying of the hw. 136 * Some fields have architecturally UNKNOWN reset values and these are 137 * set to zero. 138 * 139 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 140 * 141 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 142 * required by PSCI specification) 143 */ 144 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 145 if (GET_RW(ep->spsr) == MODE_RW_64) 146 sctlr_elx |= SCTLR_EL1_RES1; 147 else { 148 /* 149 * If the target execution state is AArch32 then the following 150 * fields need to be set. 151 * 152 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 153 * instructions are not trapped to EL1. 154 * 155 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 156 * instructions are not trapped to EL1. 157 * 158 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 159 * CP15DMB, CP15DSB, and CP15ISB instructions. 160 */ 161 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 162 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 163 } 164 165 /* 166 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 167 * and other EL2 resgisters are set up by cm_preapre_ns_entry() as they 168 * are not part of the stored cpu_context. 169 */ 170 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 171 172 /* Populate EL3 state so that we've the right context before doing ERET */ 173 state = get_el3state_ctx(ctx); 174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 175 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 176 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 177 178 /* 179 * Store the X0-X7 value from the entrypoint into the context 180 * Use memcpy as we are in control of the layout of the structures 181 */ 182 gp_regs = get_gpregs_ctx(ctx); 183 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 184 } 185 186 /******************************************************************************* 187 * The following function initializes the cpu_context for a CPU specified by 188 * its `cpu_idx` for first use, and sets the initial entrypoint state as 189 * specified by the entry_point_info structure. 190 ******************************************************************************/ 191 void cm_init_context_by_index(unsigned int cpu_idx, 192 const entry_point_info_t *ep) 193 { 194 cpu_context_t *ctx; 195 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 196 cm_init_context_common(ctx, ep); 197 } 198 199 /******************************************************************************* 200 * The following function initializes the cpu_context for the current CPU 201 * for first use, and sets the initial entrypoint state as specified by the 202 * entry_point_info structure. 203 ******************************************************************************/ 204 void cm_init_my_context(const entry_point_info_t *ep) 205 { 206 cpu_context_t *ctx; 207 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 208 cm_init_context_common(ctx, ep); 209 } 210 211 /******************************************************************************* 212 * Prepare the CPU system registers for first entry into secure or normal world 213 * 214 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 215 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 216 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 217 * For all entries, the EL1 registers are initialized from the cpu_context 218 ******************************************************************************/ 219 void cm_prepare_el3_exit(uint32_t security_state) 220 { 221 uint32_t sctlr_elx, scr_el3; 222 cpu_context_t *ctx = cm_get_context(security_state); 223 224 assert(ctx); 225 226 if (security_state == NON_SECURE) { 227 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 228 if (scr_el3 & SCR_HCE_BIT) { 229 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 230 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 231 CTX_SCTLR_EL1); 232 sctlr_elx &= ~SCTLR_EE_BIT; 233 sctlr_elx |= SCTLR_EL2_RES1; 234 write_sctlr_el2(sctlr_elx); 235 } else if (EL_IMPLEMENTED(2)) { 236 /* 237 * EL2 present but unused, need to disable safely. 238 * SCTLR_EL2 can be ignored in this case. 239 * 240 * Initialise all fields in HCR_EL2, except HCR_EL2.RW, 241 * to zero so that Non-secure operations do not trap to 242 * EL2. 243 * 244 * HCR_EL2.RW: Set this field to match SCR_EL3.RW 245 */ 246 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); 247 248 /* 249 * Initialise CPTR_EL2 setting all fields rather than 250 * relying on the hw. All fields have architecturally 251 * UNKNOWN reset values. 252 * 253 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 254 * accesses to the CPACR_EL1 or CPACR from both 255 * Execution states do not trap to EL2. 256 * 257 * CPTR_EL2.TTA: Set to zero so that Non-secure System 258 * register accesses to the trace registers from both 259 * Execution states do not trap to EL2. 260 * 261 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 262 * to SIMD and floating-point functionality from both 263 * Execution states do not trap to EL2. 264 */ 265 write_cptr_el2(CPTR_EL2_RESET_VAL & 266 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 267 | CPTR_EL2_TFP_BIT)); 268 269 /* 270 * Initiliase CNTHCTL_EL2. All fields are 271 * architecturally UNKNOWN on reset and are set to zero 272 * except for field(s) listed below. 273 * 274 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 275 * Hyp mode of Non-secure EL0 and EL1 accesses to the 276 * physical timer registers. 277 * 278 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 279 * Hyp mode of Non-secure EL0 and EL1 accesses to the 280 * physical counter registers. 281 */ 282 write_cnthctl_el2(CNTHCTL_RESET_VAL | 283 EL1PCEN_BIT | EL1PCTEN_BIT); 284 285 /* 286 * Initialise CNTVOFF_EL2 to zero as it resets to an 287 * architecturally UNKNOWN value. 288 */ 289 write_cntvoff_el2(0); 290 291 /* 292 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 293 * MPIDR_EL1 respectively. 294 */ 295 write_vpidr_el2(read_midr_el1()); 296 write_vmpidr_el2(read_mpidr_el1()); 297 298 /* 299 * Initialise VTTBR_EL2. All fields are architecturally 300 * UNKNOWN on reset. 301 * 302 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 303 * 2 address translation is disabled, cache maintenance 304 * operations depend on the VMID. 305 * 306 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 307 * translation is disabled. 308 */ 309 write_vttbr_el2(VTTBR_RESET_VAL & 310 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 311 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 312 313 /* 314 * Initialise MDCR_EL2, setting all fields rather than 315 * relying on hw. Some fields are architecturally 316 * UNKNOWN on reset. 317 * 318 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 319 * EL1 System register accesses to the Debug ROM 320 * registers are not trapped to EL2. 321 * 322 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 323 * System register accesses to the powerdown debug 324 * registers are not trapped to EL2. 325 * 326 * MDCR_EL2.TDA: Set to zero so that System register 327 * accesses to the debug registers do not trap to EL2. 328 * 329 * MDCR_EL2.TDE: Set to zero so that debug exceptions 330 * are not routed to EL2. 331 * 332 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 333 * Monitors. 334 * 335 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 336 * EL1 accesses to all Performance Monitors registers 337 * are not trapped to EL2. 338 * 339 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 340 * and EL1 accesses to the PMCR_EL0 or PMCR are not 341 * trapped to EL2. 342 * 343 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 344 * architecturally-defined reset value. 345 */ 346 write_mdcr_el2((MDCR_EL2_RESET_VAL | 347 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 348 >> PMCR_EL0_N_SHIFT)) & 349 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 350 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 351 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 352 | MDCR_EL2_TPMCR_BIT)); 353 /* 354 * Initialise HSTR_EL2. All fields are architecturally 355 * UNKNOWN on reset. 356 * 357 * HSTR_EL2.T<n>: Set all these fields to zero so that 358 * Non-secure EL0 or EL1 accesses to System registers 359 * do not trap to EL2. 360 */ 361 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 362 /* 363 * Initialise CNTHP_CTL_EL2. All fields are 364 * architecturally UNKNOWN on reset. 365 * 366 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 367 * physical timer and prevent timer interrupts. 368 */ 369 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 370 ~(CNTHP_CTL_ENABLE_BIT)); 371 } 372 } 373 374 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 375 376 cm_set_next_context(ctx); 377 } 378 379 /******************************************************************************* 380 * The next four functions are used by runtime services to save and restore 381 * EL1 context on the 'cpu_context' structure for the specified security 382 * state. 383 ******************************************************************************/ 384 void cm_el1_sysregs_context_save(uint32_t security_state) 385 { 386 cpu_context_t *ctx; 387 388 ctx = cm_get_context(security_state); 389 assert(ctx); 390 391 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 392 } 393 394 void cm_el1_sysregs_context_restore(uint32_t security_state) 395 { 396 cpu_context_t *ctx; 397 398 ctx = cm_get_context(security_state); 399 assert(ctx); 400 401 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 402 } 403 404 /******************************************************************************* 405 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 406 * given security state with the given entrypoint 407 ******************************************************************************/ 408 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 409 { 410 cpu_context_t *ctx; 411 el3_state_t *state; 412 413 ctx = cm_get_context(security_state); 414 assert(ctx); 415 416 /* Populate EL3 state so that ERET jumps to the correct entry */ 417 state = get_el3state_ctx(ctx); 418 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 419 } 420 421 /******************************************************************************* 422 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 423 * pertaining to the given security state 424 ******************************************************************************/ 425 void cm_set_elr_spsr_el3(uint32_t security_state, 426 uintptr_t entrypoint, uint32_t spsr) 427 { 428 cpu_context_t *ctx; 429 el3_state_t *state; 430 431 ctx = cm_get_context(security_state); 432 assert(ctx); 433 434 /* Populate EL3 state so that ERET jumps to the correct entry */ 435 state = get_el3state_ctx(ctx); 436 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 437 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 438 } 439 440 /******************************************************************************* 441 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 442 * pertaining to the given security state using the value and bit position 443 * specified in the parameters. It preserves all other bits. 444 ******************************************************************************/ 445 void cm_write_scr_el3_bit(uint32_t security_state, 446 uint32_t bit_pos, 447 uint32_t value) 448 { 449 cpu_context_t *ctx; 450 el3_state_t *state; 451 uint32_t scr_el3; 452 453 ctx = cm_get_context(security_state); 454 assert(ctx); 455 456 /* Ensure that the bit position is a valid one */ 457 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 458 459 /* Ensure that the 'value' is only a bit wide */ 460 assert(value <= 1); 461 462 /* 463 * Get the SCR_EL3 value from the cpu context, clear the desired bit 464 * and set it to its new value. 465 */ 466 state = get_el3state_ctx(ctx); 467 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 468 scr_el3 &= ~(1 << bit_pos); 469 scr_el3 |= value << bit_pos; 470 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 471 } 472 473 /******************************************************************************* 474 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 475 * given security state. 476 ******************************************************************************/ 477 uint32_t cm_get_scr_el3(uint32_t security_state) 478 { 479 cpu_context_t *ctx; 480 el3_state_t *state; 481 482 ctx = cm_get_context(security_state); 483 assert(ctx); 484 485 /* Populate EL3 state so that ERET jumps to the correct entry */ 486 state = get_el3state_ctx(ctx); 487 return read_ctx_reg(state, CTX_SCR_EL3); 488 } 489 490 /******************************************************************************* 491 * This function is used to program the context that's used for exception 492 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 493 * the required security state 494 ******************************************************************************/ 495 void cm_set_next_eret_context(uint32_t security_state) 496 { 497 cpu_context_t *ctx; 498 499 ctx = cm_get_context(security_state); 500 assert(ctx); 501 502 cm_set_next_context(ctx); 503 } 504