| b4ae615b | 25-Sep-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
xlat: Introduce function xlat_arch_tlbi_va_regime()
Introduce a variant of the TLB invalidation helper function that
allows the targeted translation regime to be specified, rather than
defaulting to
xlat: Introduce function xlat_arch_tlbi_va_regime()
Introduce a variant of the TLB invalidation helper function that
allows the targeted translation regime to be specified, rather than
defaulting to the current one.
This new function is useful in the context of EL3 software managing
translation tables for the S-EL1&0 translation regime, as then it
might need to invalidate S-EL1&0 TLB entries rather than EL3 ones.
Define a new enumeration to be able to represent translation regimes in
the xlat tables library.
Change-Id: Ibe4438dbea2d7a6e7470bfb68ff805d8bf6b07e5
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| f301da44 | 25-Apr-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat: Always compile TLB invalidation functions
TLB invalidation functions used to be conditionally compiled in.
They were enabled only when using the dynamic mapping feature.
because only then woul
xlat: Always compile TLB invalidation functions
TLB invalidation functions used to be conditionally compiled in.
They were enabled only when using the dynamic mapping feature.
because only then would we need to modify page tables on the fly.
Actually there are other use cases where invalidating TLBs is required.
When changing memory attributes in existing translation descriptors for
example. These other use cases do not necessarily depend on the dynamic
mapping feature.
This patch removes this dependency and always compile TLB invalidation
functions in. If they're not used, they will be removed from the binary
at link-time anyway so there's no consequence on the memory footprint
if these functions are not called.
Change-Id: I1c33764ae900eb00073ee23b7d0d53d4efa4dd21
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| fdb1964c | 28-Sep-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat: Introduce MAP_REGION2() macro
The current implementation of the memory mapping API favours mapping
memory regions using the biggest possible block size in order to
reduce the number of transla
xlat: Introduce MAP_REGION2() macro
The current implementation of the memory mapping API favours mapping
memory regions using the biggest possible block size in order to
reduce the number of translation tables needed.
In some cases, this behaviour might not be desirable. When translation
tables are edited at run-time, coarse-grain mappings like that might
need splitting into finer-grain tables. This operation has a
performance cost.
The MAP_REGION2() macro allows to specify the granularity of
translation tables used for the initial mapping of a memory region.
This might increase performance for memory regions that are likely to
be edited in the future, at the expense of a potentially increased
memory footprint.
The Translation Tables Library Design Guide has been updated to
explain the use case for this macro. Also added a few intermediate
titles to make the guide easier to digest.
Change-Id: I04de9302e0ee3d326b8877043a9f638766b81b7b
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| c64d1345 | 04-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1109 from robertovargas-arm/mem_protect
Mem protect |
| 43cbaf06 | 03-Aug-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
Add mem_region utility functions
This commit introduces a new type (mem_region_t) used to describe
memory regions and it adds two utility functions:
- clear_mem_regions: This function clears (writ
Add mem_region utility functions
This commit introduces a new type (mem_region_t) used to describe
memory regions and it adds two utility functions:
- clear_mem_regions: This function clears (write 0) to a set
of regions described with an array of mem_region_t.
- mem_region_in_array_chk This function checks if a
region is covered by some of the regions described
with an array of mem_region_t.
Change-Id: I12ce549f5e81dd15ac0981645f6e08ee7c120811
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| d4c596be | 03-Aug-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
mem_protect: Add mem_protect API
This patch adds the generic code that links the psci smc handler
with the platform function that implements the mem_protect and
mem_check_range functionalities. Thes
mem_protect: Add mem_protect API
This patch adds the generic code that links the psci smc handler
with the platform function that implements the mem_protect and
mem_check_range functionalities. These functions are optional
APIs added in PSCI v1.1 (ARM DEN022D).
Change-Id: I3bac1307a5ce2c7a196ace76db8317e8d8c8bb3f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 3388b38d | 15-Sep-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Set TCR_EL1.EPD1 bit to 1
In the S-EL1&0 translation regime we aren't using the higher VA range,
whose translation table base address is held in TTBR1_EL1. The bit
TCR_EL1.EPD1 can be used to disabl
Set TCR_EL1.EPD1 bit to 1
In the S-EL1&0 translation regime we aren't using the higher VA range,
whose translation table base address is held in TTBR1_EL1. The bit
TCR_EL1.EPD1 can be used to disable translations using TTBR1_EL1, but
the code wasn't setting it to 1. Additionally, other fields in TCR1_EL1
associated with the higher VA range (TBI1, TG1, SH1, ORGN1, IRGN1 and
A1) weren't set correctly as they were left as 0. In particular, 0 is a
reserved value for TG1. Also, TBBR1_EL1 was not explicitly set and its
reset value is UNKNOWN.
Therefore memory accesses to the higher VA range would result in
unpredictable behaviour as a translation table walk would be attempted
using an UNKNOWN value in TTBR1_EL1.
On the FVP and Juno platforms accessing the higher VA range resulted in
a translation fault, but this may not always be the case on all
platforms.
This patch sets the bit TCR_EL1.EPD1 to 1 so that any kind of
unpredictable behaviour is prevented.
This bug only affects the AArch64 version of the code, the AArch32
version sets this bit to 1 as expected.
Change-Id: I481c000deda5bc33a475631301767b9e0474a303
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| df312c5a | 21-Sep-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
xlat: simplify mmap_add_region_check parameters (#1101)
Use a mmap_region_t as parameter instead of getting a parameter for each
structure member. This reduces the scope of changes when adding memb
xlat: simplify mmap_add_region_check parameters (#1101)
Use a mmap_region_t as parameter instead of getting a parameter for each
structure member. This reduces the scope of changes when adding members
to mmap_region_t.
Also align on the convention of using mm_cursor as a variable name for
the currently inspected region when iterating on the region array.
Change-Id: If40bc4351b56c64b214e60dda27276d11ce9dbb3
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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| ea12986b | 19-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1099 from douglas-raillard-arm/dr/fix_mm_copy
xlat: fix mm copy when adding a region |
| 756f9bb8 | 15-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1094 from douglas-raillard-arm/dr/fix_mmap_add_dynamic_region
xlat: Use MAP_REGION macro as compatibility layer |
| 73addb72 | 12-Sep-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
xlat: fix mm copy when adding a region
mmap_add_region_ctx and mmap_add_dynamic_region_ctx are clearing members
that they are not aware of by copying each member one by one. Replace
this by structur
xlat: fix mm copy when adding a region
mmap_add_region_ctx and mmap_add_dynamic_region_ctx are clearing members
that they are not aware of by copying each member one by one. Replace
this by structure assignment.
Change-Id: I7c70cb408c8a8eb551402a5d8d956c1fb7f32b55
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| f18f5f98 | 13-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1092 from jeenu-arm/errata-workarounds
Errata workarounds |
| 800a55ea | 11-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1087 from robertovargas-arm/psci_do_cpu_off
Reduce time lock in psci_do_cpu_off |
| 769d65da | 31-Aug-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
xlat: Use MAP_REGION macro as compatibility layer
Use the MAP_REGION to build the mmap_region_t argument in wrappers like
mmap_add_region(). Evolution of the mmap_region_t might require adding
new m
xlat: Use MAP_REGION macro as compatibility layer
Use the MAP_REGION to build the mmap_region_t argument in wrappers like
mmap_add_region(). Evolution of the mmap_region_t might require adding
new members with a non-zero default value. Users of MAP_REGION are
protected against such evolution. This commit also protects users of
mmap_add_region() and mmap_add_dynamic_region() functions against these
evolutions.
Also make the MAP_REGION macro implementation more explicit and make it
a mmap_region_t compound literal to make it useable as a function
parameter on its own and to prevent using it in initialization of
variables of different type.
Change-Id: I7bfc4689f6dd4dd23c895b65f628d8ee991fc161
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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| 6de9b336 | 02-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7f
Cortex-A72: Implement workaround for erratum 859971
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 45b52c20 | 02-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56
Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 413115e1 | 06-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1019 from etienne-lms/log-size
CPU_DATA_LOG2SIZE depends on cache line size |
| 216e58a3 | 04-Sep-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
Reduce time lock in psci_do_cpu_off
psci_set_power_off_state only initializes a local variable, so there
isn't any reason why it should be done while the lock is held.
Change-Id: I1c62f4cd5d860d102
Reduce time lock in psci_do_cpu_off
psci_set_power_off_state only initializes a local variable, so there
isn't any reason why it should be done while the lock is held.
Change-Id: I1c62f4cd5d860d102532e5a5350152180d41d127
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 86606eb5 | 01-Sep-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size of the cpu data structure CPU_DATA_SIZE aligned on cache line size.
Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation
of function '_cpu_data_by_index'.
Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b15bab6b | 30-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs |
| 80bcf981 | 09-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained, but guarded by the
ERROR_DEPRECATED macro, so as not to break platforms that continue using
the old names.
Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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| 01ebe3d2 | 25-Aug-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1059 from kenkuang/intergration
fix a typo abort sctlr_el2 |
| 9fce2725 | 07-Aug-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table entries for a given stage of translation in
a particular translation regime. This only takes effect when ARM
Trusted Firmware is built with ARM_ARCH_MINOR >= 2.
ARM Trusted Firmware Design has been updated to include a description
of this feature usage.
Change-Id: I698305f047400119aa1900d34c65368022e410b8
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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| f45e232a | 16-Aug-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Tr
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Trusted Firmware functionality for future architecture revisions.
Replace similar usage in the current code base with the new macro.
Change-Id: I9dcd0aa71a663eabd02ed9632b8ce87611fa5a57
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 5722b78c | 23-Aug-2017 |
Alistair Francis <alistair.francis@xilinx.com> |
psci_common: Resolve GCC static analysis false positive
Previously commit 555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this
GCC issue:
services/std_svc/psci/psci_common.c: In function '
psci_common: Resolve GCC static analysis false positive
Previously commit 555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this
GCC issue:
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
This fix doesn't work as asserts aren't built in non-debug build flows.
Let's use GCCs #pragma option (documented here:
https://gcc.gnu.org/onlinedocs/gcc/Diagnostic-Pragmas.html) to avoid
this false positive instead.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
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